Large area diode co-integrated with vertical field-effect-transistors

A method for fabricating a semiconductor structure, the method comprising:

• forming a structure comprising a substrate, a source contact layer on the substrate, a first spacer layer on the source contact layer, a replacement gate on the first spacer layer, a second spacer layer on the replacement gate, and an insulating layer on the second spacer layer;
• forming a first trench in a first region of the structure, the first trench extending from a top surface of the insulating layer down to a top surface of the source contact layer;
• epitaxially growing a first channel layer up from the top surface of the source contact layer, the first channel layer filling the first trench;
• forming a second trench in a second region of the structure, the second trench extending from the top surface of the insulating layer down to the top surface of the source contact layer;
• epitaxially growing a second channel layer comprising a p- or n-type material up from the top surface of the source contact layer, the second channel layer filling the second trench, where the p- or n-type material has an opposite doping than the source contact layer to form a diode;
• recessing the first and second channel layers, the recessing leaving a first portion of the first and second channel layers above the second spacer layer;
• after the recessing, forming a first mask above and in contact with the first channel layer and forming a second mask above and in contact with second channel layer;
• after forming the first and second masks, removing the insulating layer exposing the first portion of the first and second channel layers;
• and
• performing a lateral etch of the first portion of the first and second channel layers, the lateral etch narrowing the first portion of the first and second channel layers and a second portion of the first and second channel layers below a top surface of the second spacer layer.