US 9,754,930 B2Granted

ESD protection device with improved bipolar gain using cutout in the body well

AssigneeTexas Instruments Incorporated

InventorsHenry Litzmann Edwards, Akram A. Salman

Life of this patent

Estimating the term…

Loading patent…

Abstract

An integrated circuit includes an NMOS SCR in which a p-type body well of the NMOS transistor provides a base layer for a vertical NPN layer stack. The base layer is formed by implanting p-type dopants using an implant mask which has a cutout mask element over the base area, so as to block the p-type dopants from the base area. The base layer is implanted concurrently with p-type body wells under NMOS transistors in logic components in the integrated circuit. Subsequent anneals cause the p-type dopants to diffuse into the base area, forming a base with a lower doping density that adjacent regions of the body well of the NMOS transistor in the NMOS SCR. The NMOS SCR may have a symmetric transistor, a drain extended transistor, or may be a bidirectional NMOS SCR with a symmetric transistor integrated with a drain extended transistor.

Claims3

Dependent claims

An integrated circuit, comprising:

a substrate comprising a p-type semiconductor;
a symmetric p-channel metal oxide semiconductor (PMOS) transistor disposed in said substrate;
a p-type n-channel metal oxide semiconductor (NMOS) body well disposed in said substrate;
a symmetric NMOS transistor disposed in said p-type NMOS body well;
and
an NMOS silicon controlled rectifier (SCR), including:
a p-type body well disposed in said substrate, said p-type body well having a cutout with a lower doping density;
an n-type source region disposed in said p-type body well over said cutout;
an n-type region disposed in said substrate under said cutout, said n-type region being connected to an n-type drain region;
and
a p-type body contact region, disposed in said p-type body well over said cutout;
wherein said NMOS SCR is a drain extended NMOS SCR, and wherein:
said p-type body well is a p-type drain extended body well;
a deep n-type well is disposed in said substrate, extending laterally to abut said p-type drain extended body well, so that said deep n-type well provides an extended drain of said drain extended transistor;
and
a p-type SCR contact region is disposed in said deep n-type well.

13 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/292,409Filed 13 Oct 2016 · division
Priority: 24 Aug 2012
Published: US 2017/0033096 A12 Feb 2017
Granted: 5 Sep 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification16 codes

H10D 89/713
Using bipolar transistors as protective elements: including a PNP transistor and a NPN transistor, wherein each of said transistors has its base…
H10D 84/0102
Manufacture or treatment: of thyristors having built-in components, e.g. thyristor having built-in diode
H10D 84/0191
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their doped wells
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe

Family

Application13/594,106Parent of this division · filed 24 Aug 2012
Application15/042,233Parent of this division · filed 12 Feb 2016
US 9,293,460 B2Parent of this division · filed 22 Mar 2016
US 2017/0033096 A1Pre-grant publication · published 2 Feb 2017
US 9,496,252 B2Parent of this division
US 2014/0054642 A1Published application
US 2016/0163691 A1Published application
US 9,754,930 B2This patent

From the US filing history. Foreign family members aren’t listed.