Semiconductor chip including a chip level based on a layout that includes both regular and irregular wires

A semiconductor chip including a chip level based on a layout that includes both regular and irregular wires, comprising:

• a plurality of regular wires formed within a given chip level, each of the plurality of regular wires having a linear-shape with an end-to-end length measured in a first direction substantially parallel to an underlying substrate and a side-to-side width measured in a second direction substantially parallel to the underlying substrate, the second direction perpendicular to the first direction, the plurality of regular wires positioned according to a constant pitch such that a distance as measured in the second direction between lengthwise centerlines of any two of the plurality of regular wires is an integer multiple of the constant pitch, each of the plurality of regular wires having a constant side-to-side width as measured in the second direction;
• and
• at least one irregular wire formed within the given chip level and within a region bounded by the plurality of regular wires, the at least one irregular wire having a linear-shape with an end-to-end length measured in the first direction and a side-to-side width measured in the second direction, the side-to-side width of the at least one irregular wire being direction different than the side-to-side width of the plurality of regular wires as measured in the second direction.