Designable channel FinFET fuse

#The present disclosure relates generally to the electrical, electronic and computer arts and, more particularly, to FinFET structures and their fabrication.

#Fin-type field-effect transistors (FinFETs) have three-dimensional, non-planar configurations including fin-like structures extending above substrates. The substrates may include semiconductor on insulator (SOI) substrates or bulk semiconductor substrates. Silicon fins are formed in some FinFETs on substrates via known technology such as sidewall image transfer (SIT). FinFET structures including SOI substrates can be formed, in part, by selectively etching the crystalline silicon layers down to the oxide or other insulating layers thereof following photolithography. Active fin heights are set by SOI thickness when employing SOI substrates. In bulk FinFETs, active fin height is set by oxide thickness and etched fin height. The gates of FinFETs can be formed using a “gate-first” process wherein a gate stack and spacers are formed prior to selective epitaxial growth wherein source and drain regions are enlarged. A “gate-last” process may alternatively be employed wherein the source/drain regions are formed following fin patterning. Gate-last procedures can involve making a dummy gate, fabricating other elements of the transistor such as the source/drain regions, removing the dummy gate, and replacing the removed dummy gate with actual gate materials.

#In some replacement gate processes, disposable gate level layers are deposited on a semiconductor substrate as blanket layers, i.e., as unpatterned contiguous layers. The disposable gate level layers can include, for example, a vertical stack of a disposable gate dielectric layer, a disposable gate material layer, and a disposable gate cap dielectric layer. The disposable gate dielectric layer can be, for example, a layer of silicon oxide, silicon nitride, or silicon oxynitride. The thickness of the disposable gate dielectric layer can be from 1 nm to 10 nm, although lesser and greater thicknesses can also be employed. The disposable gate material layer includes a material that can be subsequently removed selective to the dielectric material of a planarization dielectric layer to be subsequently formed. For example, the disposable gate material layer can include a semiconductor material such as a polycrystalline semiconductor material or an amorphous semiconductor material. The thickness of the disposable gate material layer can be from 30 nm to 300 nm, although lesser and greater thicknesses can also be employed. The disposable gate cap dielectric layer can include a dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride. The thickness of the disposable gate cap dielectric layer can be from 3 nm to 30 nm, although lesser and greater thicknesses can also be employed. Any other disposable gate level layers can also be employed provided that the material(s) in the disposable gate level layers can be removed selective to a planarization dielectric layer to be subsequently formed.

#The following drawings are presented by way of example only and without limitation, wherein like reference numerals (when used) indicate corresponding elements throughout the several views, and wherein:

#FIG. 1A is a schematic top plan view of an array of fins formed using a semiconductor-on-insulator substrate;

#FIG. 1B is a sectional view thereof taken along line 1B;

#It is to be appreciated that elements in the figures are illustrated for simplicity and clarity. Common but well-understood elements that may be useful or necessary in a commercially feasible embodiment may not be shown in order to facilitate a less hindered view of the illustrated embodiments.

#Principles of the present disclosure will be described herein in the context of illustrative embodiments. It is to be appreciated, however, that the specific embodiments and/or methods illustratively shown and described herein are to be considered exemplary as opposed to limiting. Moreover, it will become apparent to those skilled in the art given the teachings herein that numerous modifications can be made to the embodiments shown that are within the scope of the claims. That is, no limitations with respect to the embodiments shown and described herein are intended or should be inferred.

#One or more embodiments provide a FinFET structure wherein a semiconductor fuse is formed by a portion of a fin within a gate (channel) region. An exemplary fabrication method for forming polycrystalline fuses in one or more fin channel regions is further described.