Method of forming integrated circuit having plural transistors with work function metal gate structures

#1. Field of the Invention

#The present invention is related to a method of forming an integrated circuit, and more particularly, to a method of forming an integrated circuit having a plurality of transistors with different threshold voltages.

#2. Description of the Prior Art

#FIG. 1 to FIG. 10 are schematic diagrams of the method of forming the integrated circuit according to one embodiment of the present invention, wherein:

#FIG. 1 is a schematic diagram showing the integrated circuit at the beginning of the forming process;

#FIG. 2 is a schematic diagram showing the integrated circuit after performing a planarization process;

#To provide a better understanding of the present invention, preferred embodiments will be described in detail. The preferred embodiments of the present invention are illustrated in the accompanying drawings with numbered elements.

#Please refer to FIG. 1 to FIG. 10. FIG. 1 to FIG. 10 are schematic diagrams of the method of forming an integrated circuit according to one embodiment of the present invention. First, a substrate 300 is provided, such as a silicon substrate, a silicon-containing substrate or a silicon-on-insulator (SOI) substrate, but is not limited thereto. A plurality of shallow trench isolations (STI) 302 are disposed on the substrate 300. According to the areas encompassed by the STI 302, a first active region 400, a second active region 500 and a third active region 600, which are insulated from each other, are defined on the substrate 300. Then, a first transistor 402, a second transistor 502 and a third transistor 602 are formed on the substrate 300 in the first active region 400, the second active region 500 and the third active region 600 respectively. In one preferred embodiment of the present invention, the first transistor 402, the second transistor 502 and the third transistor 602 have the same conductive type. Preferably, they are N conductive transistors.

#In one embodiment shown in FIG. 1, the first transistor 402 includes a first interface layer 404, a first high-k dielectric layer 405, a first etch stop layer 407, a first sacrificial gate 406, a first cap layer 408, a first spacer 410, a first lightly doped drain (LDD) 412 and a first source/drain 414. In one preferred embodiment of the present invention, the first interface layer 404 can be a SiO2 layer. The first high-k dielectric layer 405 has a dielectric constant greater than 4, and the material thereof includes rare earth metal oxides or lanthanide oxides, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO), yttrium oxide (Yb2O3), yttrium silicon oxide (YbSiO), zirconium aluminate (ZrAlO), hafnium aluminate (HfAlO), aluminum nitride (AlN), titanium oxide (TiO2), zirconium oxynitride (ZrON), hafnium oxynitride (HfON), zirconium silicon oxynitride (ZrSiON), hafnium silicon oxynitride (HfSiON), strontium bismuth tantalite (SrBi2Ta2O9, SBT), lead zirconate titanate (PbZrxTi1-xO3, PZT) or barium strontium titanate (BaxSr1-xTiO3, BST), but is not limited thereto. The first etch stop layer 407 includes metal or metal/metal nitride, such as TiN. The first sacrificial gate 406 is a poly-silicon gate. In another embodiment, the first sacrificial gate 406 is a multi-layered gate including a poly-silicon layer, an amorphous silicon layer or a germanium layer. The first cap layer 408 is a SiN layer for example. The first spacer 410 can be a multi-layered structure including high temperature oxide (HTO), SiN, SiO or SiN formed by hexachlorodisilane (Si2Cl6) (HCD-SiN). The first LDD 412 and the first source/drain 414 are formed by appropriate dopants implantation. In one embodiment, the first interface layer 404 and the first etch stop layer 407 can be omitted.