MOS transistor structure and method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorPo-Yu Chen
Life of this patent
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Abstract
A method comprises depositing a first dielectric layer on a top surface of a substrate, implanting ions of a first conductivity type into the substrate, forming a first trench and a second trench in the substrate, forming a first gate in the first trench and a second gate in the second trench and forming a first drain/source region, a second drain/source region and a third drain/source region with the first conductivity type, wherein the first drain/source region and the second drain/source region are formed on opposing sides of the first gate and the third drain/source region and the second drain/source region are formed on opposing sides of the second gate.
Claims20
A method comprising:
- depositing a first dielectric layer on a top surface of a substrate;
- after the deposition of the first dielectric layer on the top surface of the substrate, implanting ions of a first conductivity type into the substrate;
- forming a first trench and a second trench in the substrate;
- forming a first gate in the first trench and a second gate in the second trench;
- forming a first drain/source region, a second drain/source region and a third drain/source region with the first conductivity type, wherein:
- the first drain/source region and the second drain/source region are formed on opposing sides of the first gate;
- and
- the third drain/source region and the second drain/source region are formed on opposing sides of the second gate;
- and
- forming a channel region with the first conductivity type in the substrate between the first drain/source region and the third drain/source region.
A method comprising:
- implanting first ions into a substrate to form a semiconductor region;
- forming a first trench and a second trench in the semiconductor region;
- forming a first gate in the first trench and a second gate in the second trench;
- implanting second ions into the semiconductor region to form a first drain/source region, a second drain/source region and a third drain/source region, wherein:
- the first ions and the second ions have a same conductivity type;
- bottoms of the first drain/source region, the second drain/source region and the third drain/source region are in contact with the semiconductor region, and wherein the first drain/source region, the second drain/source region, the third drain/source region and the semiconductor region have a same conductivity type;
- the first drain/source region and the second drain/source region are formed on opposing sides of the first gate;
- and
- the third drain/source region and the second drain/source region are formed on opposing sides of the second gate;
- forming silicide regions over the first drain/source region, the second drain/source region, the third drain/source region, the first gate and the second gate respectively;
- forming a plurality of contact plugs connected to the silicide regions;
- and
- forming a channel region having a same conductivity type as the first drain/source region, wherein the channel region, the first drain/source region, the second drain/source region and the third drain/source region form a first junction-less transistor cell.
A method comprising:
- implanting ions into a substrate to form a bulk semiconductor region;
- forming a first trench and a second trench in the bulk semiconductor region;
- forming a first gate in the first trench and a second gate in the second trench;
- forming a first drain/source region in the bulk semiconductor region;
- forming a second drain/source region in the bulk semiconductor region, wherein the first drain/source region and the second drain/source region are formed on opposing sides of the first gate;
- forming a third drain/source region in the bulk semiconductor region, the third drain/source region and the second drain/source region are formed on opposing sides of the second gate;
- and
- forming a channel region in the bulk semiconductor region, wherein the bulk semiconductor region, the channel region, the first drain/source region, the second drain/source region and the third drain/source region have a same conductivity type.
Dependencies are inferred from the claim text.