Semiconductor arrangement and formation thereof

A method of forming a semiconductor arrangement comprising:

• etching a first opening in a first dielectric layer to expose a top surface of a gate extending between a first set of fins and a second set of fins;
• etching a second opening in the first dielectric layer to expose a first metal connect overlying the first set of fins and a second metal connect overlying the second set of fins;
• forming a metal contact in the first opening;
• and
• forming a third metal connect in the second opening, wherein the third metal connect electrically couples the first metal connect to the second metal connect.

A method of forming a semiconductor arrangement comprising:

• forming a first metal connect in a first dielectric layer, wherein the first metal connect contacts a first epitaxial cap overlying a first fin;
• forming a second metal connect in the first dielectric layer, wherein:
• the second metal connect contacts a second epitaxial cap overlying a second fin spaced apart from the first fin by a shallow trench isolation (STI) material, and
• the first metal connect is separated from the second metal connect by the first dielectric layer;
• forming a second dielectric layer over the first dielectric layer, the first metal connect, and the second metal connect;
• forming a first opening in the second dielectric layer, wherein the first opening extends over the STI material and exposes the first metal connect and the second metal connect;
• and
• forming a third metal connect in the first opening, wherein the third metal connect electrically couples the first metal connect to the second metal connect.