Method of fabricating semiconductor device and computing system for implementing the method

A method of fabricating a semiconductor device, the method comprising:

• receiving a layout design in which first and second patterns formed using double patterning lithography are defined, the first pattern including a first sub pattern and a second sub pattern separated from the first sub pattern by a first gap;
• generating a first mask for exposing regions defined as the first and second sub patterns and a region between the first and second sub patterns;
• generating a second mask for exposing a region defined as the second pattern;
• and
• generating a third mask for dividing a region exposed by the first mask into the regions defined as the first and second sub patterns,
• wherein in the layout design, a region defined as the first pattern and the region defined as the second pattern are separated from each other in a first direction, and the region defined as the first sub pattern and the region defined as the second sub pattern are separated from each other in a second direction intersecting the first direction.

A method of forming patterns separated by a gap smaller than a critical dimension, the method comprising:

• forming a target layer;
• forming an insulating layer over the target layer;
• forming a first mask on the insulating layer to expose a first region extending in a first direction;
• forming a second mask to cover a second region, the second region being a region separating the first region into two sub-regions in a second direction intersecting the first direction;
• etching, using the first and second masks, the target layer to form two openings therein such that the two openings are separated by a gap corresponding to the second region, extend in the first direction, and expose underlying conductive members therethrough;
• and
• forming conductive patterns confined by the two openings such that the conductive patterns physically contact the underlying conductive members.