Memory control device and memory control method
AssigneeLapis Semiconductor Co., Ltd.
InventorToshiharu Okada
Life of this patent
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Abstract
A memory device is operative to reset write-in status or read-out status information data in accordance with a reset signal. In response to the reset signal, a memory control device refers to a power-on reset check region in a RAM and determines whether or not the received reset signal is a power-on reset signal that is the reset signal generated firstly after power on. If the reset signal is determined to be the power-on reset signal, a memory check process is executed on respective target pages in each block in the memory. A refresh process is also performed on a block in which the number of error bits detected in the memory check process is more than a threshold value. The memory check process is performed on a different page whenever power is supplied.
Claims10
A memory control device for controlling either write-in or read-out operation for a memory, the memory control device comprising:
- an interface unit connected to the memory for performing either write-in or read-out operation for the memory;
- a power-on reset signal generation unit for generating a power-on reset signal in response to power on of the memory control device;
- an internal reset signal generation unit for generating a an internal reset signal in response to a reset request;
- an initializing signal supply unit for delivering, to the interface unit, the power-on reset signal or the internal reset signal as an initializing signal that initializes write-in status or read-out status information data held by the interface unit;
- and
- a control unit for determining whether or not the initializing signal is based on the power-on reset signal after the write-in status or read-out status information data in the interface unit is initialized in response to the initializing signal, and for performing a check process on the memory if the initializing signal is determined to be based on the power-on reset signal,
- wherein the memory is divided into a plurality of blocks,
- the control unit performs the check process on some region of each of the blocks,
- the check process includes an error detection process that performs error detection on data read from the memory and generates information indicative of number of error bits, and
- the control unit executes an error correction process on a block, among the plurality of blocks, which includes data in which the number of error bits exceeds a specified threshold value.
A memory control method for controlling either write-in or read-out operation for a memory, the memory control method comprising the steps of:
- receiving an initializing signal;
- determining whether the initializing signal is a power-on reset signal generated in response to a power on or an internal reset signal generated in response to a reset request;
- and
- performing a check process on the memory only when the initializing signal is determined to be based on the power-on reset signal,
- wherein the memory is divided into a plurality of blocks, and
- in the step of performing the check process, the check process is performed on some region of each of the blocks,
- the check process includes an error detection process that performs error detection on data read from the memory and generates information indicative of number of error bits, and the method further includes the step of executing an error correction process on a block, among the plurality of blocks, which includes data in which the number of error bits exceeds a specified threshold value.
Dependencies are inferred from the claim text.