Implementing enhanced performance with read before write to phase change memory
AssigneeWestern Digital Technologies, Inc.
InventorsRobert Eugeniu Mateescu, Dejan Vucinic, Cyril Guyot
Life of this patent
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Abstract
A method and apparatus are provided for implementing enhanced performance with read before write to phase-change-memory. Each write to PCM is preceded by a read and a calculation to discover a location of any bad bits. The write data is converted to a format that can be corrected for a given number of previously undiscovered bit errors, and the writes are unverified.
Claims17
A method for implementing data write to phase-change-memory (PCM) in a system including phase-change-memory (PCM);
- a phase-change-memory (PCM) interface control coupled to said phase-change-memory (PCM);
- a controller coupled to said phase-change-memory (PCM) interface control for implementing data write to the phase-change-memory (PCM);
- said controller using said phase-change-memory (PCM) control code performing the steps of said method comprising:
- starting a data write;
- reading a group of PCM cells of the phase-change-memory (PCM) before writing to the group of cells and identifying any defective cells;
- responsive to the identified defective cells, performing a data write for data being written to the PCM using data encoding to avoid writing to the identified defective cells;
- and
- responsive to performing the data write, maintaining the written data without error checking the data write and without performing another data write for correcting any newly arising bit errors with the data write.
An apparatus for implementing data write to phase-change-memory (PCM) comprising:
- a phase-change-memory (PCM);
- a phase-change-memory (PCM) interface control coupled to said phase-change-memory (PCM);
- a controller coupled to said phase-change-memory (PCM) interface control for implementing data write to the phase-change-memory (PCM);
- phase-change-memory (PCM) control code coupled to said controller;
- said controller using said phase-change-memory (PCM) control code performing the steps:
- starting a data write;
- reading a group of PCM cells of the phase-change-memory (PCM) before writing to the group of cells and identifying any defective cells;
- responsive to the identified defective cells, performing a data write for data being written to the PCM using data encoding to avoid writing to the identified defective cells;
- and
- responsive to performing the data write, maintaining the written data without error checking the data write and without performing another data write for correcting any newly arising bit errors with the data write.
A data storage device comprising:
- a phase-change-memory (PCM);
- a phase-change-memory (PCM) interface control coupled to said phase-change-memory (PCM);
- a controller coupled to said phase-change-memory (PCM) interface control for implementing data write to the phase-change-memory (PCM);
- phase-change-memory (PCM) control code coupled to said controller;
- said controller using said phase-change-memory (PCM) control code performing the steps:
- starting a data write;
- reading a group of PCM cells of the phase-change-memory (PCM) before writing to the group of cells and identifying any defective cells;
- responsive to the identified defective cells, performing a data write for data being written to the PCM using data encoding to avoid writing to the identified defective cells;
- and
- responsive to performing the data write, maintaining the written data without error checking the data write and without performing another data write for correcting any newly arising bit errors with the data write.
Dependencies are inferred from the claim text.