Memory cell and corresponding device

A memory cell, comprising:

• a plurality of storage elements for redundantly storing an input data logic signal, said plurality of storage elements having output lines for outputting a plurality of logic signals and inputs for receiving a storage element clock signal;
• a majority vote logic circuit coupled to receive the plurality of logic signals and generate an output signal having a logic state of as a majority of said plurality of logic signals;
• a clock logic circuit configured to generate said storage element clock signal from a cell clock signal;
• and
• a multiplexing circuit having a first input coupled to a data input, a second input coupled to receive said output signal and an output generating the input data logic signal.

A memory cell, comprising:

• a plurality of storage elements for redundantly storing an input data logic signal, said plurality of storage elements having output lines for outputting a plurality of logic signals and inputs for receiving a storage element clock signal;
• a majority vote logic circuit coupled to receive the plurality of logic signals and generate an output signal having a logic state of as a majority of said plurality of logic signals;
• and
• an exclusive logic sum circuit configured to detect when one of said logic signals on said output lines undergoes a logic value transition and in response thereto assert storage element clock signal to refresh storing of the input data logic signal.