Method and device for compact eFuse array
AssigneesSemiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
InventorChia Chi Yang
Life of this patent
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Abstract
An electrical fuse (eFuse) array includes eFuse cells arranged in multiple rows and columns. Each eFuse cell has an eFuse, a first diode, and a second diode coupled to an internal node, each eFuse cell further having first, second, and third terminals coupled, respectively, to the first diode, the second diode, and the eFuse. The eFuse array further includes a shared NMOSFET for each of the multiple rows, with a drain coupled to the third terminal of each of the plurality of eFuse cells in that row and a gate coupled to a word line. Each column includes a write bit line coupled to the second terminal of each of the eFuse cells in that column, and a read bit line coupled to the first terminal of the eFuse cell.
Claims20
An electrical fuse (eFuse) memory device, comprising:
- an eFuse array having a plurality of electrical fuse (eFuse) cells arranged in multiple rows and columns, each eFuse cell having an eFuse, a first diode, and a second diode coupled to an internal node, each eFuse cell further having first, second, and third terminals, wherein:
- the first diode is coupled between the first terminal and the internal node;
- the second diode is coupled between the second terminal and the internal node;
- and
- the eFuse is coupled between the third terminal and the internal node;
- a shared NMOSFET for each of the multiple rows, with a drain coupled to the third terminal of each of the plurality of eFuse cells in that row, a source coupled to a ground terminal, and a gate coupled to a word line;
- a write bit line for each column, the write bit line coupled to the second terminal of each of the eFuse cells in that column;
- and
- a read bit line for each column, the read bit line coupled to the first terminal of the eFuse cell.
An electrical fuse (eFuse) cell, comprising:
- first, second, and third terminals;
- an eFuse;
- and
- a PNP bipolar transistor having a first P-type region, an N-type base region, and a second P-type region;
- wherein:
- the first terminal is coupled to the first P-type region and configured for coupling to a read bit line;
- the second terminal is coupled to the second P-type region and configured for coupling to a write bit line;
- and
- the eFuse is coupled between the third terminal and the N-type base region of the bipolar transistor, the third terminal being configured for coupling to a shared NMOSFET, and the shared NMOSFET being configured for coupling to the third terminals of all eFuse cells in a row of an array.
An electrically programmable fuse (eFuse) cell, comprising:
- first, second, and third terminals;
- an eFuse;
- a first diode;
- and
- a second diode;
- wherein:
- the eFuse, the first diode, and the second diode are coupled to an internal node,
- the first diode is coupled between the first terminal and the internal node;
- the second diode is coupled between the second terminal and the internal node;
- the eFuse is coupled between the third terminal and the internal node;
- the first terminal is configured for coupling to a read bit line;
- the second terminal is configured for coupling to a write bit line;
- and
- the third terminal is configured for coupling to a shared NMOSFET, the shared NMOSFET configured for coupling to the third terminals of all eFuse cells in a row of an array.
Dependencies are inferred from the claim text.