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US 9,754,674 B2Granted
Concurrently reading first and second pages of memory cells having different page addresses
AssigneeMicron Technology, Inc.
InventorsViolante Moschiano, Mattia Cichocki, Tommaso Vali, Maria-Luisa Gallese, Umberto Siciliani
Life of this patent
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Abstract
In an embodiment, a first page of memory cells in a first memory plane is read concurrently with a second page of memory cells in a second memory plane. The second memory plane is different than the first memory plane, but is in the same memory array as the first memory plane. The second page of memory cells has a different page address than the first page of memory cells.
Claims20
A method of operating a memory device, comprising:
- using a first digital-to-analog converter to respectively generate one or more first analog read voltages from one or more first digital values successively received at the first digital-to-analog converter;
- successively applying the one or more first analog read voltages, as the one or more first analog read voltages are generated, to a first page of memory cells in a first memory plane;
- using a second digital-to-analog converter to respectively generate one or more second analog read voltages from one or more second digital values successively received at the second digital-to-analog converter;
- successively applying the one or more second analog read voltages, as the one or more second analog read voltages are generated, to a second page of memory cells in a second memory plane;
- selecting one of a plurality of first conversion tables dedicated to a first portion of a page buffer for output and selecting one of a plurality of second conversion tables dedicated to a second portion of the page buffer for output;
- outputting a first code to the first portion of the page buffer from a location in the selected first conversion table that is identified by a particular first digital data value of the one or more first digital values in response to a first memory cell of the first page of memory cells conducting in response to a particular first analog read voltage of the one or more first analog read voltages that is generated from the particular first digital data value;
- and
- outputting a second code to the second portion of the page buffer from a location in the selected second conversion table that is identified by a particular second digital data value of the one or more second digital values in response to a second memory cell of the second page of memory cells conducting in response to a particular second analog read voltage of the one or more second analog read voltages that is generated from the particular second digital data value;
- wherein the first page of memory cells in the first memory plane and the second page of memory cells in the second memory plane have different page addresses;
- and
- wherein the first and second codes are output concurrently.
8 more elements
A method of operating a memory device, comprising:
- using a first digital-to-analog converter to respectively generate one or more first analog read voltages from one or more first digital values successively received at the first digital-to-analog converter;
- successively applying the one or more first analog read voltages, as the one or more first analog read voltages are generated, to a first page of memory cells in a first memory plane;
- using a second digital-to-analog converter to respectively generate one or more second analog read voltages from one or more second digital values successively received at the second digital-to-analog converter;
- successively applying the one or more second analog read voltages, as the one or more second analog read voltages are generated, to a second page of memory cells in a second memory plane;
- selecting a first one of a plurality of first conversion tables dedicated to a first portion of a page buffer for output and selecting a first one of a plurality of second conversion tables dedicated to a second portion of the page buffer for output;
- selecting a second one of the plurality of first conversion tables dedicated to the first portion of the page buffer for output and selecting a second one of the plurality of second conversion tables dedicated to the second portion of the page buffer for output;
- outputting a first code to the first portion of the page buffer from a location in the selected first one of the plurality of first conversion tables that is identified by a particular first digital data value of the one or more first digital values in response to a first memory cell of the first page of memory cells conducting in response to a particular first analog read voltage of the one or more first analog read voltages that is generated from the particular first digital data value;
- outputting a second code to the second portion of the page buffer from a location in the selected first one of the plurality of second conversion tables that is identified by a particular second digital data value of the one or more second digital values in response to a second memory cell of the second page of memory cells conducting in response to a particular second analog read voltage of the one or more second analog read voltages that is generated from the particular second digital data value;
- outputting a third code to the first portion of the page buffer from a location in the selected second one of the plurality of first conversion tables that is identified by the particular first digital data value of the one or more first digital values in response to the first memory cell of the first page of memory cells conducting in response to the particular first analog read voltage of the one or more first analog read voltages that is generated from the particular first digital data value;
- and
- outputting a fourth code to the second portion of the page buffer from a location in the selected second one of the plurality of second conversion tables that is identified by the particular second digital data value of the one or more second digital values in response to the second memory cell of the second page of memory cells conducting in response to the particular second analog read voltage of the one or more second analog read voltages that is generated from the particular second digital data value;
- wherein the first page of memory cells in the first memory plane and the second page of memory cells in the second memory plane have different page addresses;
- and
- wherein the first and second codes are output concurrently.
11 more elements
A method of operating a memory device, comprising:
- using a first digital-to-analog converter to respectively generate one or more first analog read voltages from one or more first digital values successively received at the first digital-to-analog converter from a counter;
- successively applying the one or more first analog read voltages, as the one or more first analog read voltages are generated, to a first page of memory cells in a first memory plane;
- using a second digital-to-analog converter to respectively generate one or more second analog read voltages from one or more second digital values successively received at the second digital-to-analog converter from the counter;
- successively applying the one or more second analog read voltages, as the one or more second analog read voltages are generated, to a second page of memory cells in a second memory plane;
- selecting a first one of a plurality of first conversion tables dedicated to a first portion of a page buffer for output and selecting a first one of a plurality of second conversion tables dedicated to a second portion of the page buffer for output;
- selecting a second one of the plurality of first conversion tables dedicated to the first portion of a page buffer for output and selecting a second one of the plurality of second conversion tables dedicated to the second portion of the page buffer for output;
- outputting a first code to the first portion of the page buffer from a location in the selected first one of the plurality of first conversion tables that is identified by a particular first digital data value of the one or more first digital values in response to a first memory cell of the first page of memory cells conducting in response to a particular first analog read voltage of the one or more first analog read voltages that is generated from the particular first digital data value, wherein the first code comprises an upper page bit corresponding to a particular state of the first memory cell;
- outputting a second code to the second portion of the page buffer from a location in the selected first one of the plurality of second conversion tables that is identified by a particular second digital data value of the one or more second digital values in response to a second memory cell of the second page of memory cells conducting in response to a particular second analog read voltage of the one or more second analog read voltages that is generated from the particular second digital data value, wherein the second code comprises an upper page bit corresponding to a particular state of the second memory cell;
- outputting a third code to the first portion of the page buffer from a location in the selected second one of the plurality of first conversion tables that is identified by the particular first digital data value of the one or more first digital values in response to the first memory cell of the first page of memory cells conducting in response to the particular first analog read voltage of the one or more first analog read voltages that is generated from the particular first digital data value, wherein the third code comprises a lower page bit corresponding to the particular state of the first memory cell;
- and
- outputting a fourth code to the second portion of the page buffer from a location in the selected second one of the plurality of second conversion tables that is identified by the particular second digital data value of the one or more second digital values in response to the second memory cell of the second page of memory cells conducting in response to the particular second analog read voltage of the one or more second analog read voltages that is generated from the particular second digital data value, wherein the fourth code comprises a lower page bit corresponding to the particular state of the second memory cell;
- wherein the first page of memory cells in the first memory plane and the second page of memory cells in the second memory plane have different page addresses;
- and
- wherein the first and second codes are output concurrently.
11 more elements
Dependencies are inferred from the claim text.