Method of initializing and driving 3D non-volatile memory device using time varying erase signal

A method of driving a 3D non-volatile memory device, the 3D non-volatile memory device comprising a plurality of string selection lines, a plurality of wordlines, a ground selection line, and a plurality of memory layers, each of the memory layers comprising a plurality of channel lines respectively coupled to bitlines via first ends of the plurality of channel lines and coupled to a common source line via second ends of the plurality of channel lines, wherein the plurality of string selection lines, the plurality of wordlines, and the ground selection line intersect with the plurality of channel lines, and each of the plurality of channel lines defines a memory string and the memory string has string selection transistors respectively coupled with the plurality of string selection lines, the method comprising:

• initially leveling threshold voltages of string selection transistors disposed in one or more of the plurality of memory layers to have a predetermined target level;
• applying a first time varying erase voltage signal having a first time varying section to a first plurality of channel lines of a first memory layer, the first memory layer being one of the plurality of memory layers, the initially leveled string selection transistors including a first plurality of string selection transistors in the first memory layer;
• setting threshold voltages of the first plurality of string selection transistors in the first memory layer by controlling each of the plurality of string selection lines coupled with the first plurality of string selection transistors during a first time interval corresponding to the first time varying section of the first time varying erase voltage signal;
• selecting a second memory layer, the second memory layer being one of the plurality of memory layers;
• and
• programming a selected memory cell of a selected memory string among a plurality of memory strings of the selected second memory layer by applying a bitline program voltage to a bitline coupled to the selected memory string, applying a program inhibition voltage higher than the bitline program voltage to bitlines coupled to unselected memory strings, and applying a program voltage to a wordline coupled to the selected memory cell.