Nonvolatile semiconductor memory device which performs improved erase operation
AssigneeToshiba Memory Corporation
InventorsJun Nakai, Noboru Shibata
Life of this patent
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Abstract
According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.
Claims37
A method of controlling a nonvolatile semiconductor memory device including a memory cell array including a plurality of blocks, each of the blocks including a plurality of memory cells, the method comprising:
- performing an erase operation to a selected block, the erase operation including a first phase, a second phase, a third phase, a fourth phase, a fifth phase, and a sixth phase;
- performing a first operation supplying a first erase voltage to the selected block and performing a first verify operation supplying a first verify voltage to the selected block, in the first phase;
- performing a second operation supplying a second erase voltage to the selected block and performing a second verify operation supplying a second verify voltage to the selected block, in the second phase after the first phase, the second erase voltage being higher than the first erase voltage;
- performing a third operation supplying a third erase voltage to the selected block, in the third phase after the second phase and interrupting the erase operation when receiving a first command for interrupting the erase operation during the third operation, the third erase voltage being higher than the second erase voltage;
- performing a third verify operation supplying a third verify voltage to the selected block when receiving a second command for resuming the erase operation after the third phase, in the fourth phase after the third phase;
- performing a fourth operation supplying a fourth erase voltage to the selected block and performing a fourth verify operation supplying a fourth verify voltage to the selected block, in the fifth phase after the fourth phase;
- and
- performing a fifth operation supplying a fifth erase voltage to the selected block and performing a fifth verify operation supplying a fifth verify voltage to the selected block, in the sixth phase after the fifth phase, the fourth erase voltage and the fifth erase voltage being equal to or higher than the third erase voltage.
A method of controlling a nonvolatile semiconductor memory device including a memory cell array including a plurality of memory cells, the method comprising:
- erasing data of the memory cells;
- interrupting an erase operation of the memory cells and holding an erase condition before the interrupting in accordance with a first command during the erase operation;
- resuming the erase operation in accordance with a second command;
- and
- outputting a status to an outside in accordance with a third command when receiving the third command after the interrupting the erase operation and before the resuming the erase operation,
- wherein the status relates to whether the erase operation has passed or failed at a point of the interrupting.
A method of controlling a nonvolatile semiconductor memory device including a memory cell array including a plurality of memory cells, the method comprising:
- holding one of read data and data to be written in the memory cell array;
- performing read, write, and erase of data for the memory cells;
- executing the one of a read operation and a write operation to interrupt an erase operation when receiving a command that instructs one of the read operation and the write operation during the erase operation;
- outputting a status to an outside in accordance with a first command when receiving the first command after interrupting the erase operation and before resuming the erase operation;
- and
- resuming the erase operation in accordance with a second command, and
- wherein the status relates to whether the erase operation has passed or failed at a point of the interrupting.
A method of controlling a nonvolatile semiconductor memory device including a memory cell array including a plurality of blocks including a plurality of memory cells, the method comprising:
- performing an erase operation including a first operation and a second operation, the first operation including supplying a first erase voltage to a selected block;
- interrupting the erase operation when receiving a first command for interrupting the erase operation;
- and
- performing the second operation when receiving a second command for resuming the erase operation, the second operation including supplying a second erase voltage to the selected block, the second erase voltage being higher than the first erase voltage.
Dependencies are inferred from the claim text.