Flash memory arrangement with a common read-write circuit shared by partial matrices of a memory column

A flash memory arrangement for non-volatile memory comprising:

• a first memory cell in a first memory column and a third memory cell in a third memory column connected to a first discharge hub and via respective first bit circuits to respective first read-write circuits;
• a second memory cell in a second memory column and a fourth memory cell in a fourth memory column connected to a second discharge hub and via respective first bit circuits to respective second read-write circuits,
• the first read-write circuits being controlled by a first column decoder and the second read-write circuits being controlled by a second column decoder;
• the first memory cell and the third memory cell being connected to the first discharge hub and the second memory cell and the fourth memory cell being connected to the second discharge hub, alternatingly;
• and each of the first and second read-write circuits comprising a write latch, a read amplifier, a bit circuit pre-charge circuit and a databus interface,
• and each of the first, second, third and fourth memory cells being also connected to a word circuit, a gate control circuit and a select circuit,
• and each of the first and second read-write circuits being also connected to a databus and a read control signal circuit,
• wherein each of the first, second, third and fourth memory cells is arranged in a first partial matrix and comprises a first select transistor, a memory transistor and a second select transistor, with the second select transistor connected to the select circuit and controlled by a global, non-address-decoded read-write signal,
• the first partial matrix further including a reference memory cell connected to each of the first bit circuits,
• the flash memory arrangement further including a second partial matrix having a reference memory cell connected to each of second bit circuits,
• and each of the first and second read-write circuits is connected to a respective one of the first bit circuits of the first partial matrix and to a respective one of the second bit circuits of the second partial matrix,
• and a reference memory cell of the second partial matrix is addressed to determine if a logical one or zero is included, in a read mode, in each of the first, second, third and fourth memory cells,
• and the first and second read-write circuits are controlled by a global read control signal supplied by the read control signal circuit.