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US 9,754,668 B1Granted
Digital perceptron
AssigneeFlashsilicon Incorporation
InventorLee Wang
Life of this patent
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Abstract
In view of the neural network information parallel processing, a digital perceptron device analogous to the build-in neural network hardware systems for parallel processing digital signals directly by the processor's memory content and memory perception in one feed-forward step is disclosed. The digital perceptron device of the invention applies the configurable content and perceptive non-volatile memory arrays as the memory processor hardware. The input digital signals are then broadcasted into the non-volatile content memory array for a match to output the digital signals from the perceptive non-volatile memory array as the content-perceptive digital perceptron device.
Claims17
A digital perceptron device, comprising:
- a non-volatile content memory array having m rows by n columns of first memory cells for parallel comparing a n-bit input symbol with a number m of n-bit non-volatile content symbols pre-configured in the m rows of first memory cells respectively having m first output nodes, wherein each of the m first output nodes generates an indication signal indicative of whether the n-bit input symbol matches its pre-configured n-bit non-volatile content symbol;
- a match detector circuit having m detector cells that are respectively connected to the m first output nodes and that have m second output nodes, wherein each of the m detector cells generates a digital switching signal at its second output node after receiving a corresponding indication signal;
- a non-volatile perceptive memory array having m rows by q columns of second memory cells, wherein the m rows of second memory cells are respectively connected to the m second output nodes and pre-configured with a number m of q-bit non-volatile perceptive symbols, wherein a received digital switching signal with a first voltage level switches on a corresponding row of second memory cells to output a corresponding q-bit non-volatile perceptive symbol as a q-bit output symbol, wherein a received digital switching signal with a second voltage level switches off a corresponding row of second memory cells, and wherein m, n and q are greater than one;
- wherein each of the m rows by n columns of first memory cells and the m rows by q columns of second memory cells comprises a non-volatile memory (NVM) device pair, and each NVM device pair outputs one of a high operating voltage VDD and a ground voltage VSS of the digital perceptron device in response to two input voltages VDD and VSS,
- wherein the digital perceptron device further comprises
- an output bus;
- and
- an output buffer and driver unit located between bit lines of the non-volatile perceptive memory array and the output bus for temporarily storing the q-bit output symbol and amplifying the q-bit output symbol signal to drive the output bus, wherein whether the output buffer and driver unit is electrically connected to the bit lines of the non-volatile perceptive memory array depends on a first control signal, and whether the output buffer and driver unit is electrically connected to the output bus depends on a second control signal;
- and
- wherein the second control signal is activated when the n-bit input symbol matches one of the number m of pre-configured n-bit non-volatile content symbols.
7 more elements
A method for operating a digital perceptron device comprising a non-volatile content memory array and a non-volatile perceptive memory array, the method comprising:
- parallel comparing an n-bit input symbol with a number m of n-bit non-volatile content symbols pre-configured in the non-volatile content memory array having m rows by n columns of first memory cells so that each of the m rows of first memory cells generates an indication signal indicative of whether the n-bit input symbol matches its pre-configured n-bit non-volatile content symbol;
- respectively obtaining m digital switching signals according to m indication signals;
- respectively receiving the m digital switching signals by m rows of second memory cells in the non-volatile perceptive memory array having m rows by q columns of second memory cells, wherein the m rows of second memory cells are respectively pre-configured with a number m of q-bit non-volatile perceptive symbols;
- switching on a corresponding row of second memory cells to output a corresponding q-bit non-volatile perceptive symbol as a q-bit output symbol in response to one digital switching signal having a first voltage level;
- and
- switching off a corresponding row of second memory cells in response to one digital switching signal having a second voltage level, wherein m, n and q are greater than one;
- wherein each of the m rows by n columns of first memory cells and the m rows by q columns of second memory cells comprises a non-volatile memory (NVM) device pair, and each NVM device pair outputs one of a high operating voltage VDD and a ground voltage VSS of the digital perceptron device in response to two input voltages VDD and VSS,
- wherein the method further comprises:
- temporarily storing the q-bit output symbol according to a first control signal;
- amplifying the q-bit output symbol to obtain a q-bit output signal;
- and
- outputting the q-bit output signal in response to a second control signal, wherein the second control signal is activated when the n-bit input symbol matches one of the number m of pre-configured n-bit non-volatile content symbols.
9 more elements
Dependencies are inferred from the claim text.