Semiconductor device

A semiconductor device comprising:

• a semiconductor substrate having a main surface;
• a first semiconductor region of first conductivity type formed over the main surface of the semiconductor substrate;
• an element isolation region formed over the main surface of the semiconductor substrate;
• a first active region and a second active region located in the first semiconductor region and surrounded by the element isolation region;
• a first insulating film formed over the main surface of the semiconductor substrate in the first active region;
• a semiconductor layer formed over the first insulating film;
• a first conductor layer formed over the semiconductor layer through a second insulating film;
• a pair of second semiconductor regions of second conductivity type opposite to the first conductivity type, formed in the semiconductor layer at both ends of the first conductor layer;
• a second conductor layer formed over the semiconductor layer through a third insulating film in the first active region;
• a third semiconductor region of the first conductivity type formed over a surface of the first semiconductor region in the second active region;
• a fourth insulating film covering the first conductor layer and the second conductor layer;
• a first wiring lying over the fourth insulating film and extending so as to lie over the second conductor layer;
• and
• a second wiring coupled with the third semiconductor region through the first wiring,
• wherein the second conductor layer is electrically floating.

A semiconductor device comprising:

• a semiconductor substrate having a main surface;
• a plurality of word lines extending in a first direction and a plurality of bit line pairs extending in a direction perpendicular to the first direction over the main surface of the semiconductor substrate;
• an SRAM memory cell located at an intersection between the word line and the bit line pair;
• a first memory array and a second memory array which have the SRAM memory cells arranged in a matrix pattern and are located adjacent to each other along the second direction;
• a power supply region located between the first memory array and the second memory array, extending in the first direction;
• a first and a second load transistor, a first and a second driver transistor, and a first and a second access transistor which configure the SRAM memory cell;
• an n-type well region in which the first load transistor is located and which extends across the first memory array, the power supply region, and the second memory array in the second direction;
• a first active region located in the n-type well region, extending in the second direction in the first memory array and the power supply region;
• a second active region located in the n-type well region and isolated from the first active region in the power supply region;
• a first gate electrode layer extending in the first direction and crossing the first active region in the first memory array;
• a second gate electrode layer extending in the first direction and crossing the first active region in the power supply region;
• a semiconductor layer formed over the n-type well region of the first active region through a first insulating film in the first memory array and the power supply region;
• a gate electrode of the first load transistor as part of the first gate electrode layer, formed over the semiconductor layer through a second insulating film in the first memory array;
• a pair of p-type semiconductor regions formed in the semiconductor layer at both ends of the gate electrode of the first load transistor in the first active region of the first memory array;
• a third insulating film formed between the semiconductor layer and the second gate electrode layer in the first active region of the power supply region;
• an n-type semiconductor region formed over a surface of the n-type well region in the second active region of the power supply region;
• and
• a power supply wiring extending in the first direction and being coupled with the n-type semiconductor region in the power supply region,
• wherein the second gate electrode layer is electrically floating.