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US 9,754,659 B2Granted
Low-power semiconductor device
AssigneeRenesas Electronics Corporation
InventorsMasanao Yamaoka, Koichiro Ishibashi, Shigezumi Matsui, Kenichi Osada
Life of this patent
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Abstract
A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.
Claims8
A semiconductor device comprising:
- a first power line for a first power voltage;
- a second power line for a second power voltage different from the first power voltage;
- a circuit block including a first node coupled to the first power line, a second node and a plurality of flip-flop circuits;
- a memory circuit block including a first node coupled to the first power line, a second node coupled to the second power line and a plurality of Static Random Access Memory (SRAM) cells;
- and
- a Metal-Oxide-Semiconductor (MOS) switch coupled between the second node of the circuit block and the second power line, wherein, while a power supply of the second power voltage to the plurality of flip-flop circuits is cut off by the MOS switch, the plurality of SRAM cells are supplied with the second voltage from the second power line, and a part of information held in the plurality of flip-flop circuits is transferred to the plurality of SRAM cells before the MOS switch is changed to an off status.
3 more elements
Dependencies are inferred from the claim text.