Semiconductor device, memory device, electronic device, and method for driving semiconductor device

A method for driving a semiconductor device comprising:

• a memory cell comprising a first transistor and a capacitor;
• and
• a second transistor,
• wherein the first transistor comprises an oxide semiconductor in a channel formation region,
• wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,
• wherein the other of the source and the drain of the first transistor is electrically connected to one of electrodes of the capacitor,
• wherein the other of the electrodes of the capacitor is electrically connected to a second wiring, and
• wherein a gate of the second transistor is electrically connected to the first wiring,
• the method comprising the steps of:
• performing a first operation of supplying a first potential based on data to be written to the memory cell to the second wiring;
• performing a second operation of supplying a predetermined potential to the one of the electrodes of the capacitor by turning on the first transistor;
• performing a third operation of turning off the first transistor after performing the first operation and the second operation;
• and
• performing a fourth operation of setting a potential of the one of the electrodes of the capacitor to a third potential by changing a potential of the second wiring from the first potential to a second potential after performing the third operation.

A semiconductor device comprising:

• a memory cell comprising a first transistor and a capacitor;
• a read circuit comprising a second transistor;
• and
• a control circuit comprising a third transistor,
• wherein the first transistor comprises an oxide semiconductor in a channel formation region,
• wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,
• wherein the other of the source and the drain of the first transistor is electrically connected to one of electrodes of the capacitor,
• wherein the other of the electrodes of the capacitor is electrically connected to a second wiring,
• wherein a gate of the second transistor is electrically connected to the first wiring,
• wherein one of a source and a drain of the third transistor is electrically connected to the first wiring, and
• wherein the memory cell, the read circuit and the control circuit are stacked with each other.