Master/slave control voltage buffering

#Some embodiments relate generally to circuits for buffering analog control voltages.

#Embodiments of the invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements.

#FIG. 1 is a diagram generally showing a master-slave clock generation system using voltage controlled delay lines in accordance with some embodiments.

#FIG. 2 is a diagram generally showing a DDR system with master DLL and slave VCDLs in accordance with some embodiments.

#In some embodiments, disclosed herein are approaches for facilitating voltage controlled slaved (or replica) clock circuits such as voltage controlled delay lines (VCDLs) off of a master clock generator. In such systems, one or more control (or bias) voltages are generated to control a master clock generator such as a master DLL. One or more “slave” circuits may be controlled off of the master's control voltage so that their clocks replicate desired traits of the master clock.

#Systems typically use buffers to provide the control voltages to the slave clk circuits so that the master control voltage is not detrimentally loaded down or otherwise altered. Unfortunately, buffer characteristics can fluctuate, depending on design, and process, voltage and temperature fluctuations, so trimming functionality is ideally provided to make adjustments as needed. Traditional buffer trimming methods commonly use voltage domain approaches such as is well known with the use of comparators and reference voltages. However, such methods usually require excessive analog circuitry and rely on voltage accuracy. Accordingly, improved approaches would be desired.

#In some embodiments, buffers using current mirrors may be used to provide reasonably accurate high input/low output impedance buffers for generating master control voltage copies without unduly loading the control voltage themselves. Moreover, in some embodiments, trimming approaches, e.g., using time-domain, rather than voltage-domain, comparisons may be employed. Such approaches may be used, for example, for master/slave DLLs in memory interfaces such as in DDR memory interface circuits.