Dynamically controlling voltage for access operations to magneto-resistive random access memory (MRAM) bit cells to account for process variations

A method of measuring process variation of magneto-resistive random access memory (MRAM) bit cells in an MRAM array, comprising:

• receiving a supply voltage coupled to the MRAM array;
• coupling the supply voltage from a supply voltage input to a magnetic tunnel junction (MTJ) process variation measurement circuit (PVMC), comprising one or more MTJ circuits each comprising:
• a measurement transistor of a metal oxide semiconductor (MOS) type of an access transistor in at least one MRAM bit cell in the MRAM array;
• a measurement MTJ device of a type of an MTJ device in the at least one MRAM bit cell in the MRAM array, the measurement MTJ device coupled to the measurement transistor;
• and
• generating a process variation measurement voltage signal representing process variation in the measurement transistor and the measurement MTJ device of the one or more MTJ circuits, representing process variation of the access transistor and the MTJ device in the at least one MRAM bit cell in the MRAM array, as a function of the supply voltage coupled to the MTJ PVMC.

A memory system, comprising:

• a power management circuit configured to generate a supply voltage;
• a magneto-resistive random access memory (MRAM) array coupled to the supply voltage, the MRAM array comprised of a plurality of MRAM bit cells, each MRAM bit cell among the plurality of MRAM bit cells comprising a magnetic tunnel junction (MTJ) device coupled to an access transistor;
• and
• an MRAM bit cell process variation measurement circuit (PVMC) for determining process variation in the plurality of MRAM bit cells in the MRAM array, the MRAM bit cell PVMC comprising an MTJ PVMC comprising:
• a supply voltage input configured to receive the supply voltage generated by the power management circuit;
• one or more MTJ circuits each comprising:
• a measurement transistor of a metal oxide semiconductor (MOS) type of the access transistor in at least one MRAM bit cell among the plurality of MRAM bit cells in the MRAM array;
• and
• a measurement MTJ device of a type of the MTJ device in the at least one MRAM bit cell among the plurality of MRAM bit cells in the MRAM array, the measurement MTJ device coupled to the measurement transistor;
• and
• an MTJ measurement output;
• the MTJ PVMC configured to generate, on the MTJ measurement output, a process variation measurement voltage signal representing process variation in the measurement transistor and the measurement MTJ device of the one or more MTJ circuits, representing process variation of the access transistor and the MTJ device in the at least one MRAM bit cell among the plurality of MRAM bit cells in the MRAM array, as a function of the supply voltage coupled to the MTJ PVMC;
• the power management circuit further configured to:
• receive the process variation measurement voltage signal from the MRAM bit cell PVMC;
• determine a supply voltage level based on the received process variation measurement voltage signal;
• and
• dynamically generate the supply voltage at the determined supply voltage level.