Memory device and system supporting command bus training, and operating method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsHye-Ran Kim, Tae-Young Oh
Life of this patent
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Abstract
A memory device and system supporting command bus training are provided. An operating method of the memory device includes entering into a command bus training mode, receiving a clock signal, a chip selection signal and a first command/address signal, generating an internal clock signal by dividing the clock signal, generating a second command/address signal by latching the first command/address signal at a rising edge or a falling edge of the internal clock signal when a chip selection signal is activated, and outputting the second command/address signal.
Claims18
A command bus training method in a system in which a command/address signal and a clock signal are provided to a memory device from a memory controller, the command bus training method comprising:
- entering into a command bus training mode at the memory device;
- generating an internal clock signal in the memory device by dividing the clock signal;
- transmitting a first command/address signal by the memory controller;
- transmitting a chip selection signal by the memory controller, the chip selection signal having an adjustable delay with respect to the internal clock signal;
- generating and transmitting by the memory device, a second command/address signal by latching the first command/address signal at a rising edge or a falling edge of the internal clock signal, when the chip selection signal is activated;
- comparing the first command/address signal with the second command/address signal by the memory controller;
- and
- determining a delay of the chip selection signal based on a plurality of comparison results corresponding to the adjustable delay of the chip selection signal.
An operating method of a memory device supporting command bus training, the operating method comprising:
- entering into a mode of the command bus training;
- receiving a clock signal, a chip selection signal and a first command/address signal;
- generating first and second internal clock signals by dividing the clock signal, each of the first and second internal clock signals having the same frequency and different phases with respect to each other;
- generating a second command/address signal by latching the first command/address signal at a rising edge or a falling edge of one of the first and second internal clock signals when the chip selection signal is activated;
- and
- outputting the second command/address signal to an outside of the memory device,
- wherein the generating of the first and second internal clock signals comprises selecting one of the first and second internal clock signals in response to a phase selection signal,
- wherein the memory device is connected to a memory controller through a command/address bus and a data bus, and
- wherein the phase selection signal is received through at least one signal line of the data bus or is transmitted to a data mask pad of the memory device.
A method of command bus training for a semiconductor device, the method comprising:
- receiving a clock signal having a first frequency;
- generating internal clock signals based on the clock signal, each of the internal clock signals having a second frequency and different phases with respect to each other, wherein the second frequency is smaller than the first frequency;
- a) receiving a first command/address signal having variable delays with respect to a first internal clock signal of the internal clock signals;
- b) generating a second command/address signal based on the first command/address signal and the first internal clock signal;
- c) comparing the first command/address signal with the second command/address signal;
- repeating a), b), and c) with a different delay of the variable delays;
- and
- determining a delay of the first command/address signal based on the comparison results.
Dependencies are inferred from the claim text.