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US 9,754,649 B2Granted
Memory system with command mixing for timing control
AssigneeSamsung Electronics Co., Ltd.
InventorsSeung-Jun Shin, Tae-Young Oh
Life of this patent
Estimating the term…
Abstract
A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.
Claims17
A memory system, comprising:
- a memory controller to selectively operate in a first mode and a second mode, the memory controller to transmit a first command continuously during a plurality of clock cycles in the first mode and the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command in the second mode;
- and
- a memory to change command latch timing depending on the first mode or the second mode.
A memory system, comprising:
- a memory controller to selectively operate in a first mode and a second mode, the memory controller to transmit an active command including a row address continuously during a plurality of clock cycles in the first mode and the memory controller to mix a column address strobe (CAS) command including a column address with the active command and transmit a mixture of the active command and the CAS command in the second mode;
- and
- a memory device to change command latch timing depending on the first mode or the second mode.
An apparatus, comprising:
- an interface coupled to a memory;
- and
- a memory controller to selectively operate in a first mode and a second mode, the memory controller to transmit a first command continuously through the interface during a plurality of clock cycles in the first mode and to mix a second command with the first command and transmit the mixture of the first command and the second command through the interface in the second mode, wherein the memory controller is to insert the second command between the clock cycles of the first command in the second mode.
Dependencies are inferred from the claim text.