Apparatuses and methods for memory operations having variable latencies

An apparatus, comprising:

• a memory array having memory cells;
• a memory operation controller configured to receive memory instructions and decode the same to provide internal signals for performing memory operations for the memory instructions, the memory operation controller further configured to wait a predetermined hold-off period following performance of the memory operations, to await additional memory instructions, before resuming a suspended memory operation;
• and
• a register configured to store a maximum variable latency period, wherein the register is configured to store a maximum variable latency period for write operations and store a maximum variable latency period for read operations.

An apparatus, comprising:

• a memory array having memory cells;
• a write buffer configured to store write data to be written to the memory array;
• a memory operation controller configured to receive memory instructions and decode the same to provide internal signals for performing memory operations for the memory instructions, the memory operation controller further configured to provide an acknowledgement indicative of an end of the variable latency period;
• a register coupled to the memory operation controller and configured to store information related to a hold-off period following completion of a read operation to await additional memory instructions before resuming a suspended write operation and further configured to store a maximum variable latency period, wherein the register is configured to store a maximum variable latency period for write operations and store a maximum variable latency period for read operations.

A method, comprising:

• receiving at a memory a read instruction and an address from which read data is to be read;
• during a variable latency period for the read instruction, suspending a write operation responsive to the read instruction;
• providing an acknowledgement indicative of an end of the variable latency period;
• providing the read data for the read instruction;
• continuing to suspend the write operation for a hold-off period following completion of the read operation, wherein the memory waits for additional memory instructions during the hold-off period;
• receiving another read instruction during the hold-off period;
• further suspending the write operation responsive to receiving the another read instruction;
• and
• performing a read operation for the another read instruction and restarting the hold-off period at the end of the read operation.