Three-dimensional semiconductor device with top dummy cells, bottom dummy cells and operating method thereof

An operating method of a semiconductor device, the operating method comprising:

• performing an erase operation on a memory block including source selection transistors, bottom dummy cells, a plurality of memory cells, top dummy cells and drain selection transistors arranged in a vertical direction with respect to a semiconductor substrate, wherein the bottom dummy cells are disposed under the memory cells and the top dummy cells are disposed over the memory cells;
• simultaneously increasing threshold voltages of the bottom dummy cells and the top dummy cells by applying a first soft program voltage to a bottom dummy word line coupled to the bottom dummy cells and a second soft program voltage greater than the first soft program voltage to a top dummy word line coupled to the top dummy cells;
• verifying the top and bottom dummy cells;
• and
• repeatedly performing the erase operation and increasing the threshold voltages of the bottom dummy cells and the top dummy cells at a same time by gradually increasing the first and second soft program voltages until the verifying of the top and bottom dummy cells passes.

A semiconductor device, comprising:

• a memory block including bottom dummy cells and top dummy cells stacked in a vertical direction with respect to a semiconductor substrate and memory cells stacked between the bottom dummy cells and the top dummy cells;
• a peripheral circuit configured for erasing the memory block and performing a soft program operation;
• and
• a control circuit configured for controlling the peripheral circuit to apply a first soft program voltage to bottom dummy word lines coupled to the bottom dummy cells disposed under the memory cells, and a second soft program voltage greater than the first soft program voltage to top dummy word lines coupled to the top dummy cells disposed over the memory cells during the soft program operation.