US 9,754,646 B1 · Voltage stress tolerant high speed memory driver having flying capacitor circuit

Abstract

Embodiments relate to circuits, electronic design automation (EDA) circuit layouts, systems, methods, and computer readable media to enable logic devices operating on a core supply voltage to drive memory devices operating on a different supply voltage using low power and high data rates while avoiding voltage over-stress of thin-oxide transistors. In an embodiment, channels of a thin-oxide PMOS transistor, a thick-oxide PMOS transistor, a thick-oxide NMOS transistor, and a thin-oxide NMOS transistor are coupled in order from a memory device voltage supply rail to a low voltage supply rail. Gates of the thin-oxide PMOS transistor and the thick-oxide NMOS transistor are coupled with an output of a flying capacitor circuit that level-shifts an input signal by a difference between the memory device supply and core supply voltages, while gates of the thick-oxide PMOS transistor and the thin-oxide NMOS transistor receive the input signal via a buffer.

Claims19

Dependent claims

A computer memory driver circuit comprising:

thin-oxide PMOS transistor, a thick-oxide PMOS transistor, a thick-oxide NMOS transistor, and a thin-oxide NMOS transistor having channels coupled in order from a first high voltage rail to a low voltage rail, the coupling between the thick-oxide PMOS transistor and the thick-oxide NMOS transistor at an output node to drive a computer memory circuit;
a flying capacitor circuit having an input to receive an input signal and an output coupled with a gate of the thin-oxide PMOS transistor and a gate of the thick-oxide NMOS transistor, the flying capacitor circuit also coupled to the first high voltage rail and a second high voltage rail, the flying capacitor to level-shift the input signal by a difference between a voltage of the first high voltage rail and a voltage of the second high voltage rail;
and
a buffer circuit having an input to receive the input signal and an output coupled with a gate of the thick-oxide PMOS transistor and a gate of the thin-oxide NMOS transistor.

1 more element

A method of driving a computer memory circuit, the method comprising:

applying a voltage from a first high voltage rail to a channel of a thin-oxide PMOS transistor coupled with channels of a thick-oxide PMOS transistor, a thick-oxide NMOS transistor, and a thin-oxide NMOS transistor in order from the first high voltage rail to a low voltage rail, the thin-oxide PMOS transistor also coupled with the first high voltage rail and the thin-oxide NMOS transistor also coupled with the low voltage rail, the coupling between the thick-oxide PMOS transistor and the thick-oxide NMOS transistor to drive a driver circuit output;
responsive to receiving an input signal at an input of a flying capacitor circuit, applying an output voltage from the flying capacitor circuit to a gate of the thin-oxide PMOS transistor and a gate of the thick-oxide NMOS transistor, the flying capacitor circuit also coupled to the first high voltage rail and a second high voltage rail;
and
responsive to receiving the input signal at an input of a buffer circuit, applying an output voltage from the buffer circuit to a gate of the thick-oxide PMOS transistor and a gate of the thin-oxide NMOS transistor;
wherein the flying capacitor circuit is configured to level-shift the output voltage applied to the gates of the thin-oxide PMOS transistor and the thick-oxide NMOS transistor relative to the input signal, an amount of the level shift being a difference between a voltage of the first high voltage rail and a voltage of the second high voltage rail.

2 more elements

A non-transitory computer readable medium comprising instructions that, when executed by one or more processors of a computing device, cause the computing device to perform operations comprising:

selecting elements of a flying capacitor circuit to couple with a first high voltage rail having a first high voltage level and a second high voltage rail having a second high voltage level, the flying capacitor circuit to level-shift an input signal received at an input node by a difference between the first high voltage level and the second high voltage level and provide the level-shifted input signal at a flying capacitor circuit output;
selecting elements of a buffer circuit to couple between the input node and a buffer circuit output;
configuring a thin-oxide PMOS transistor to have a source coupled with the first high voltage rail and a gate coupled with the flying capacitor circuit output;
configuring a thick-oxide PMOS transistor to have a source coupled with a drain of the thin-oxide PMOS transistor, a drain coupled with an output node, and a gate coupled with the buffer circuit output;
configuring a thin-oxide NMOS transistor to have a source coupled with the low voltage rail and a gate coupled with the buffer circuit output;
configuring a thick-oxide NMOS transistor to have a source coupled with a drain of the thin-oxide NMOS transistor, a drain coupled with the output node, and a gate coupled with the flying capacitor circuit output;
and
generating a circuit design file comprising the flying capacitor circuit, the buffer circuit, the thin-oxide PMOS transistor, the thick-oxide PMOS transistor, the thick-oxide NMOS transistor, and the thin-oxide NMOS transistor.

5 more elements

Dependencies are inferred from the claim text.

Voltage stress tolerant high speed memory driver having flying capacitor circuit

Life of this patent

Voltage stress tolerant high speed memory driver having flying capacitor circuit

Life of this patent

Abstract

Claims19