Bit line charging for a device
AssigneeSanDisk Technologies LLC
InventorsAnirudh Amarnath, Tai-Yuan Tseng
Life of this patent
Estimating the term…
Abstract
An apparatus includes a first bit line coupled to a first storage element and a second bit line coupled to a second storage element. A first bit line charging circuit is coupled to the first bit line and is configured to charge the first bit line to a first bias voltage of multiple bias voltages based on a first programming state. A second bit line charging circuit is coupled to the second bit line and is configured to charge the second bit line to a second bias voltage of the multiple bias voltages based on a second programming state. The second programming state is different than the first programming state.
Claims16
An apparatus comprising:
- a group of storage elements including a first storage element and a second storage element;
- a first bit line coupled to the first storage element;
- a second bit line coupled to the second storage element;
- a first bit line charging circuit coupled to the first bit line, the first bit line charging circuit configured to charge the first bit line to a first bias voltage of multiple bias voltages based on a first programming state;
- a second bit line charging circuit coupled to the second bit line, the second bit line charging circuit configured to charge the second bit line to a second bias voltage of the multiple bias voltages based on a second programming state, the second programming state different than the first programming state;
- a supply node;
- and
- a supply transistor coupled to the supply node and configured to receive multiple supply voltages from the supply node.
An apparatus comprising:
- means for storing a value;
- means for charging a bit line coupled to the means for storing;
- and
- means for increasing a voltage in voltage steps that correspond to multiple voltages and for applying one of multiple voltages to a gate of the means for charging to charge the bit line to one of multiple bit line voltages to enable programming of the means for storing using a single programming pulse, the multiple voltages corresponding to a set of programming states.
A system comprising:
- a controller;
- and
- at least one memory die coupled to the controller, the at least one memory die comprising:
- a group of storage elements comprising a first storage element;
- a group of bit lines coupled to the group of storage elements, the group of bit lines comprising a first bit line coupled to the first storage element;
- a group of bit line charging circuits coupled to the group of storage elements and to the group of bit lines, the group of bit line charging circuits comprising a first bit line charging circuit coupled to the first bit line;
- a counter configured to store a counter value associated with a cycle of a bit line charging process to charge the group of bit lines;
- a set of latches configured to receive data from the controller, the data indicating a programming state for the first storage element;
- and
- a comparison circuit coupled to the counter and to the set of latches, the comparison circuit configured to decouple the first bit line from a supply voltage in response to the counter value indicating a cycle of the bit line charging process that corresponds corresponding to the programming state.
Dependencies are inferred from the claim text.