Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorTeruo Takagiwa
Life of this patent
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Abstract
A semiconductor memory device includes a plurality of memory cells, a data bus connected to a first column of the memory cells, by which data is transferred to and from the memory cells of the first column, a data latch storing data indicating whether the first column is defective or not, and a transistor having a first terminal connected to the data bus, a second terminal connected to a voltage source, and a gate connected to an output of the data latch.
Claims7
A semiconductor memory device comprising:
- a plurality of memory cells;
- a data bus connected to a first column of the memory cells, by which data is transferred to and from the memory cells of the first column;
- a data latch storing data indicating whether the first column is defective or not;
- a transistor having a first terminal connected to the data bus, and a second terminal connected to an output of the data latch, the transistor being turned on during a test operation to store data indicating whether or not the first column is defective or not;
- a plurality of sense amplifier latches connected between the first column of memory cells and the data bus;
- and
- an operation circuit configured to compare data stored in the sense amplifier latches with expected values to determine whether or not the first column is defective or not.
The device according to 1, wherein the test operation includes multiple test stages and at the conclusion of each test stage, an interim result indicating whether or not the first column is defective or not is stored in the data latch.
Dependencies are inferred from the claim text.