Memory device and reference circuit thereof

A method comprising:

• generating, by a first reference storage unit, a first signal having a first logic state via a first reference data line in a condition that a first reference switch of a plurality of reference switches is turned on;
• generating, by a second reference storage unit, a second signal having a second logic state via a second reference data line in a condition that a second reference switch of the reference switches is turned on;
• and
• determining, by a sensing unit, a logic state of bit data of a corresponding memory cell of a plurality of memory cells coupled to a data line according to the first signal and the second signal,
• wherein a number of the reference switches which are coupled to one of the first reference data line or the second reference data line is the same as a number of the memory cells coupled to the data line.

A device, comprising:

• a plurality of memory cells coupled to a data line, wherein each of the memory cells is configured to store bit data;
• a plurality of reference switches;
• a plurality of reference storage units configured to be biased by the reference switches to generate a first signal via a first reference data line and to generate a second signal via a second reference data line, wherein the first signal and the second signal have different logic states, and a number of the reference switches which are coupled to one of the first reference data line or the second reference data line is the same as a number of the memory cells coupled to the data line;
• and
• a sensing unit configured to determine a logic state of the bit data of the memory cell according to the first signal and the second signal.