Gate controlling unit, gate controlling circuit, array substrate and display panel

A gate controlling unit, comprising:

• a gate driving subunit configured for driving a gate line;
• a first reset subunit configured for resetting the gate driving subunit after the gate driving subunit finishes driving the gate line;
• and
• a suspension and resumption subunit configured for controlling the gate driving subunit to suspend and resume the gate driving subunit;
• wherein
• the first reset subunit comprises:
• a tenth transistor and a first reset signal input terminal, wherein, a gate electrode of the tenth transistor is electrically connected with the first reset signal input terminal, a drain electrode of the tenth transistor is electrically connected with a first node of the gate driving subunit, and a source electrode of the tenth transistor is electrically connected with a second level signal input terminal of the gate driving subunit;
• and
• the suspension and resumption subunit comprises:
• an eleventh transistor and a third trigger signal input terminal, wherein, a gate electrode of the eleventh transistor is electrically connected with the third trigger signal input terminal, a drain electrode of the eleventh transistor is electrically connected with a second level signal input terminal of the gate driving subunit, and a source electrode of the eleventh transistor is electrically connected with a gate electrode of a seventh transistor of the gate driving subunit.