Gate drive apparatus and display apparatus

A display apparatus, comprising a gate drive apparatus, the gate drive apparatus comprising N shift register units,

• wherein, a forward select signal terminal of a p-th shift register unit receives a signal output by a (p−2)-th shift register unit, wherein p=3, 4, . . . , N, and a backward select signal terminal of an r-th shift register unit receives a signal output by an (r+2)-th shift register unit, wherein r=1, 2, . . . , N−2;
• a forward select signal terminal of a first shift register unit receives a first initial trigger signal, and a forward select signal terminal of a second shift register unit receives a second initial trigger signal;
• and if N is an even number, then the backward select signal terminal of the (N−1)-th shift register unit receives the first initial trigger signal, and the backward select signal terminal of the N-th shift register unit receives the second initial trigger signal;
• and if N is an odd number, then the backward select signal terminal of the N-th shift register unit receives the first initial trigger signal, and the backward select signal terminal of the (N−1)-th shift register unit receives the second initial trigger signal;
• wherein a clock block signal terminal of a k-th shift register unit receives a mod((k−1)/4)-th clock signal, wherein k=1, 2, . . . , N;
• a signal received by backward scan signal terminal of each of the shift register units other than the last and second last shift register units is a same signal received by a clock block signal terminal of a succeeding shift register unit, a backward scan signal terminal of the second last shift register unit receives a mod((mod((N−2)/4)+2)/4)-th clock signal, and a backward scan signal terminal of the last shift register unit receives a mod((mod((N−1)/4)+2)/4)-th clock signal;
• when a 0th clock signal is at the high level, the second clock signal is at the low level, and when the second clock signal is at the high level, the 0th clock signal is at the low level;
• when a first clock signal is at the high level, the third clock signal is at the low level, and when the third clock signal is at the high level, the first clock signal is at the low level;
• and a period of time in which an n-th clock signal is at the high level overlaps with a period of time in which an (n+1)-th clock signal is at the high level by a length of time no less than a second preset length of time, wherein n=0, 1, 2, 3, and when n+1>3, the (n+1)-th clock signal is a mod((n+1)/4)-th clock signal, and
• wherein in backward scanning, if N is an odd number, then a period of time in which the first initial trigger signal is at the high level overlaps with the period of time in which the mod((mod((N−1)/4)+2)/4)-th clock signal is at the high level at a time by a length of time no less than a period of time it takes to charge a gate of a transistor of a drive gate line in the N-th shift register unit to a voltage at which the transistor can be turned on stably and no more than one cycle of the mod((mod((N−1)/4)+2)/4)-th clock signal, and a period of time in which the second initial trigger signal is at the high level overlaps with the period of time in which the mod((mod((N−2)/4)+2)/4)-th clock signal is at the high level at a time by a length of time no less than a period of time it takes to charge a gate of a transistor of a drive gate line in the (N−1)-th shift register unit to the voltage at which the transistor can be turned on stably and no more than one cycle of the mod((mod((N−2)/4)+2)/4)-th clock signal;
• and if N represents an even number, then the period of time in which the first initial trigger signal is at the high level overlaps with the period of time in which the mod((mod((N−2)/4)+2)/4)-th clock signal is at the high level at a time by a length of time no less than a period of time it takes to charge the gate of the transistor of the drive gate line in the (N−1)-th shift register unit to the voltage at which the transistor can be turned on stably and no more than one cycle of the mod((mod((N−2)/4)+2)/4)-th clock signal, and the period of time in which the second initial trigger signal is at the high level overlaps with the period of time in which the mod((mod((N−1)/4)+2)/4)-th clock signal is at the high level at a time by a length of time no less than a period of time it takes to charge the gate of the transistor of the drive gate line in the N-th shift register unit to the voltage at which the transistor can be turned on stably and no more than one cycle of the mod((mod((N−1)/4)+2)/4)-th clock signal.