Display driver
AssigneeLapis Semiconductor Co., Ltd.
InventorHijiri Shirasaki
Life of this patent
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Abstract
A display driver is provided which can prevent concentration of currents flowing into a display device and display a high-quality image without uneven luminance. A plurality of delayed clock signals used to apply a plurality of pixel driving voltages to data lines of the display device at respective different timings are generated by a DLL circuit including a variable delay circuit group constituted by variable delay circuits are connected in series, and a phase comparator that detects a phase difference of a delayed clock signal with respect to a reference clock signal and adjusts a delay amount of each of the variable delay circuits so that the phase difference converges to zero.
Claims8
A display driver which drives a display device, by applying K (K is an integer greater than or equal to 2) pixel driving voltages corresponding to pixel-by-pixel luminance levels indicated by an image data signal to K data lines of said display device, respectively, said driver comprising:
- a delayed clock generation part configured to generate first to t-th (t is an integer less than or equal to K and greater than or equal to 2) delayed clock signals having phases different from each other and being synchronized with a reference clock signal;
- an output enable signal generation part configured to generate first to K-th output enable signals on the basis of said first to t-th delayed clock signals, wherein said output enable signal generation part includes a shift register including first to K-th flip-flops connected in series, wherein said first to K-th flip-flops are each supplied with any one of said first to t-th delayed clock signals, and wherein outputs of said first to K-th flip-flops serve as said first to K-th output enable signals respectively;
- and
- an output part configured to apply the K pixel driving voltages to the K data lines at respective different timings on the basis of said first to K-th output enable signals,
- wherein:
- said delayed clock generation part includes a phase comparator and a variable delay circuit group constituted by first to (t+1)-th variable delay circuits each having a basic delay time which is one (t+1)-th of a period of said reference clock signal are connected in series with each other;
- said reference clock signal is supplied to the first variable delay circuit;
- outputs of the first to t-th variable delay circuits in said variable delay circuit group serve as said first to t-th delayed clock signals respectively;
- and
- said phase comparator adjusts a delay time of each of the first to t-th variable delay circuits in the variable delay circuit group on the basis of a phase difference between a signal output from the (t+1)-th variable delay circuit and said reference clock signal.
A display driver which drives a display device, comprising:
- a first driver for applying first to K-th (K is n/2 and n is an integer greater than or equal to 2) pixel driving voltages among the first to an n-th pixel driving voltages corresponding to pixel-by-pixel luminance levels indicated by an image data signal to first to K-th data lines of the display device, respectively;
- and
- a second driver for applying a (K+1)-th to the n-th pixel driving voltages among said first to n-th pixel driving voltages to (K+1)-th to n-th data lines of the display device, respectively, wherein:
- the first and second drivers each include
- a delayed clock generation part configured to generate first to t-th (t is an integer less than or equal to K and greater than or equal to 2) delayed clock signals having phases different from each other and being synchronized with a reference clock signal;
- an output enable signal generation part configured to generate first to K-th output enable signals on the basis of said first to t-th delayed clock signals, wherein said output enable signal generation part includes a shift register including first to K-th flip-flops connected in series, wherein said first to K-th flip-flops are each supplied with any one of said first to t-th delayed clock signals, and wherein outputs of said first to K-th flip-flops serve as said first to K-th output enable signals respectively;
- and
- an output part configured to apply the K pixel driving voltages to the K data lines at respective different timings on the basis of said first to K-th output enable signals,
- wherein:
- said delayed clock generation part includes a phase comparator and a variable delay circuit group constituted by first to (t+1)-th variable delay circuits each having a basic delay time which is one (t+1)-th of a period of said reference clock signal are connected in series with each other;
- said reference clock signal is supplied to the first variable delay circuit;
- outputs of the first to t-th variable delay circuits in said variable delay circuit group serve as said first to t-th delayed clock signals respectively;
- and
- said phase comparator adjusts a delay time of each of the first to t-th variable delay circuits in the variable delay circuit group on the basis of a phase difference between a signal output from the (t+1)-th variable delay circuit and said reference clock signal.
Dependencies are inferred from the claim text.