Layout optimization for integrated circuit design

A method comprising:

• with a computing system, receiving a target pattern;
• decomposing the target pattern into a main pattern and an original cut pattern, the original cut pattern comprising a plurality of cut features;
• with the computing system, associating a keep-out-zone with each of the plurality of cut features;
• decomposing, based on the keep-out-zones associated with each of the plurality of cut features, the original cut pattern into a first cut pattern associated with a first mask and a second cut pattern associated with a second mask;
• and
• fabricating an integrated circuit using the first mask and the second mask, the first mask being different than the second mask.

A method comprising:

• receiving a target pattern;
• receiving a set of constraints, the set of constraints being associated with decomposition of the target pattern into a main pattern, a first cut pattern associated with a first mask, and a second cut pattern associated with a second mask;
• with a computing system, checking the target pattern for compliance with a first constraint of the set of constraints, the first constraint associated with the first cut pattern;
• with the computing system, checking the target pattern for compliance with a second constraint of the set of constraints, the second constraint associated with the second cut pattern, the second constraint being different than the first constraint;
• with the computing system, modifying the pattern to create a modified target pattern in response to determining that a violation of either the first constraint or the second constraint is found during the checking;
• and
• fabricating, with the first mask and the second mask, an integrated circuit associated with the modified target pattern.