Path-based floorplan analysis
AssigneeSynopsys, Inc.
InventorRussell B. Segal
Life of this patent
Estimating the term…
Abstract
Systems and techniques for computing a timing effort metric are described. According to one definition, the computed timing effort metric indicates a level of difficulty of fixing a timing violation associated with a timing path between two circuit objects in a circuit design layout.
Claims17
In an electronic design automation (EDA) tool in a computer, a method for displaying a placed circuit design in a graphical user interface (GUI) of the EDA tool, the method comprising:
- the EDA tool in the computer computing an intrinsic path slack of a timing path between two circuit objects in the placed circuit design;
- the EDA tool in the computer computing a physical distance between the two circuit objects in the placed circuit design;
- the EDA tool in the computer computing a timing effort metric based on the intrinsic path slack and the physical distance, wherein the intrinsic path slack of the timing path between the two circuit objects does not change when the physical distance between the two circuit objects is changed in the placed circuit design;
- and
- the EDA tool in the computer displaying a GUI element associated with the timing path between the two circuit objects in the placed circuit design, wherein the displayed GUI element has a visual attribute that is based on the timing effort metric of the timing path.
A non-transitory computer-readable storage medium storing instructions of an electronic design automation (EDA) tool that, when executed by a computer, cause the computer to perform a method for displaying a placed circuit design in a graphical user interface (GUI) of the EDA tool, the method comprising:
- computing an intrinsic path slack of the timing path between the two circuit objects in the placed circuit design;
- computing a physical distance between the two circuit objects in the placed circuit design;
- computing a timing effort metric based on an intrinsic path slack and the physical distance, wherein the intrinsic path slack of the timing path between the two circuit objects does not change when the physical distance between the two circuit objects is changed in the placed circuit design;
- and
- displaying a GUI element associated with the timing path between the two circuit objects in the placed circuit design, wherein the displayed GUI element has a visual attribute that is based on the timing effort metric of the timing path.
An apparatus, comprising:
- a processor;
- and
- a non-transitory computer-readable storage medium storing instructions of an electronic design automation (EDA) tool that, when executed by the processor, cause the apparatus to perform a method for displaying a placed circuit design in a graphical user interface (GUI) of the EDA tool, the method comprising:
- computing an intrinsic path slack of a timing path between the two circuit objects in the placed circuit design;
- computing a physical distance between the two circuit objects in the placed circuit design;
- computing a timing effort metric based on the intrinsic path slack and the physical distance, wherein the intrinsic path slack of the timing path between the two circuit objects does not change when the physical distance between the two circuit objects is changed in the placed circuit design;
- and
- displaying a GUI element associated with the timing path between the two circuit objects in the placed circuit design, wherein the displayed GUI element has a visual attribute that is based on the timing effort metric of the timing path.
Dependencies are inferred from the claim text.