Integrated circuit design method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChuan-Fang Su, Kun-Zhi Chung, Yuan-Hsiang Lung
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChuan-Fang Su, Kun-Zhi Chung, Yuan-Hsiang Lung
Estimating the term…
An IC design method includes: receiving a first layout including a first pattern; receiving a second layout including a second pattern, the first pattern separated from the second pattern when overlapping the first layout and the second layout; providing a cut pattern between the first pattern and the second pattern and overlapping the first pattern when overlapping the first layout, the second layout and the cut pattern; and providing a jog extending from the cut pattern to further overlap the first pattern with a length when a spacing between the second pattern and an edge of the cut pattern overlapping the first pattern is lower than a predetermined value, in which a ratio of the length of the jog to the spacing between the second pattern and the edge of the cut pattern overlapping the first pattern is in a range of 1/5 to 1/1.
An integrated circuit (IC) design method, the method comprising:
An IC design method, the method comprising:
An IC design method, the method comprising:
Dependencies are inferred from the claim text.
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Circuit design at the physical level: design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or…
Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles…
Circuit design at the physical level: floor-planning or layout, e.g. partitioning or placement
Computing and data processing
About 8 years 3 months of term left · ends 20 Jan 2035 (estimated)
The semiconductor integrated circuit (IC) industry has experienced rapid growth. In semiconductor manufacturing, functional density is generally increasing with reduced geometry size, and smaller and more complex integrated circuits than the previous generation are produced. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. However, such scaling down also increases the processing and manufacturing complexity of integrated circuits. For these advances to be realized, associated developments are required in the processing and manufacturing of the integrated circuits.
For example, as IC technologies are continually progressing to smaller technology nodes, such as 65 nm technology node, 45 nm technology node, 20 nm technology node and below, simply scaling down similar designs used at larger feature sizes often results in poorly shaped or poorly arranged device features. Typically, optical proximity correction (OPC) may be performed on a design pattern before the pattern is created on a mask. Nevertheless, current OPC techniques may not offer great enough fidelity or sufficient rules to correct problems in sub-45 nm designs. Therefore, although existing methods for improving IC manufacturing have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
FIG. 1 is a top view of an exemplified first layout in accordance with some embodiments of the present disclosure.
FIG. 2 is a top view of an exemplified second layout in accordance with some embodiments of the present disclosure.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
An integrated circuit (IC) manufacturing system includes a plurality of entities, such as a design house, a mask house, and an IC fabrication entity (i.e., a fab), that interact with one another in the design, development, and manufacturing cycles and/or services related to manufacturing an IC device. The plurality of entities are connected by a communications network, which may be a single network or a variety of different networks, such as an intranet and the Internet, and may include wired and/or wireless communication channels. Each entity may interact with other entities and may provide services to and/or receive services from the other entities. The design house, mask house, and IC fabrication entity may be a single entity or separate entities.