Reducing dynamic clock skew and/or slew in an electronic circuit

A system to reduce dynamic clock skew and/or slew in a digital electronic circuit caused by varying physical parameters, the system comprising:

• a memory;
• and
• a processing device communicatively coupled to the memory, wherein the system performs a method comprising:
• referencing a layout database and/or a netlist of a design for the digital electronic circuit before its manufacturing, the design comprising a clock mesh having adjacent sub-meshes driven by at least partially disjoint clock trees and connecting outputs of leaf level drivers in the design, the clock trees being driven by a common root tree, wherein clock trees of adjacent sub-meshes are connected at a given level (L(n)) by a shorting bar (SB), and wherein the sub-meshes contain dummy buffers at a level (L(m)) equal or higher than the shorting bar level (L(n));
• modifying the digital electronic circuit design to reduce dynamic clock skew and/or slew, including:
• identifying a set of neighboring buffer pairs (BP(i)) each comprising active buffers in adjacent sub-meshes, which are connected by the shorting bar (SB);
• for each neighboring buffer pair (BP(i)) of the set:
• placing a dummy buffer for each of their active buffers in the adjacent sub-meshes close to the active buffers;
• routing an input of a first dummy buffer located in a first sub-mesh to an output of an active buffer in a second sub-mesh;
• routing an input of a second dummy buffer located in the second sub-mesh to an output of an active buffer in the first sub-mesh;
• and
• connecting inputs of the first and second dummy buffers to the shorting bar (SB).

A computer program product for reducing dynamic clock skew and/or slew in a digital electronic circuit caused by varying physical parameters, the computer program product comprising:

• a computer readable storage medium having computer readable program instructions embodied therewith, the computer readable program instructions being executable by a processor to perform a method comprising:
• referencing a layout database and/or a netlist of a design for the digital electronic circuit before its manufacturing, the design comprising a clock mesh having adjacent sub-meshes driven by at least partially disjoint clock trees and connecting outputs of leaf level drivers in the design, the clock trees being driven by a common root tree, wherein clock trees of adjacent sub-meshes are connected at a given level (L(n)) by a shorting bar (SB), and wherein the sub-meshes contain dummy buffers at a level (L(m)) equal or higher than the shorting bar level (L(n));
• modifying the digital electronic circuit design to reduce dynamic clock skew and/or slew, including:
• identifying a set of neighboring buffer pairs (BP(i)) each comprising active buffers in adjacent sub-meshes, which are connected by the shorting bar (SB);
• for each neighboring buffer pair (BP(i)) of the set:
• placing a dummy buffer for each of their active buffers in the adjacent sub-meshes close to the active buffers;
• routing an input of a first dummy buffer located in a first sub-mesh to an output of an active buffer in a second sub-mesh;
• routing an input of a second dummy buffer located in the second sub-mesh to an output of an active buffer in the first sub-mesh;
• and
• connecting inputs of the first and second dummy buffers to the shorting bar (SB).