Method and device for programming a FPGA

A device for programming a FPGA, wherein said FPGA comprises an array of macrocells, each comprising at least a configurable hardware block and a configurable interconnection network, the device comprising:

• at least one de-virtualizing module, configured for converting a high-level configuration file into a bitstream file whose format depends on the architecture of the FPGA;
• and
• at least one logic mapping module, configured for uploading a said bitstream file at a predetermined location of a configuration memory of the FPGA;
• wherein said high-level configuration file contains:
• first data defining a set of macrocells and their relative positions;
• second data defining a configuration of the hardware blocks of said macrocells;
• and
• third data defining interconnections between said macrocells;
• and it contains neither data defining an absolute position of said macrocells within the FPGA, nor local routing information fully defining a configuration of their interconnection networks.

A semiconductor chip comprising a FPGA and a device for programming said FPGA, wherein the FPGA comprises an array of macrocells, each comprising at least a configurable hardware block and a configurable interconnection network, and the device comprises:

• at least one de-virtualizing module, configured for converting a high-level configuration file into a bitstream file whose format depends on the architecture of the FPGA;
• and
• at least one logic mapping module, configured for uploading a said bitstream file at a predetermined location of a configuration memory of the FPGA;
• wherein said high-level configuration file contains
• first data defining a set of macrocells and their relative positions;
• second data defining a configuration of the hardware blocks of said macrocells;
• and
• third data defining interconnections between said macrocells;
• and it contains neither data defining an absolute position of said macrocells within the FPGA, nor local routing information fully defining a configuration of their interconnection networks.