US 9,754,059 B2Granted

Graphical design verification environment generator

AssigneeVtool Ltd.

InventorsHagai Arbel, Asi Lifshitz

Life of this patent

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Abstract

A graphical tool creates design-verification environments. The tool includes a graphical environment builder that allows for the drag and drop addition of verification IP (“VIP”) modules to a graphical verification environment. The tool assigns connector signals associated with source code that simulates a connection between a VIP module and the device under test (“DUT”). The tool learns which connection signals are suitable to connect a VIP to the DUT and facilitates selecting of the suitable signals in the environment development process. The tool converts the graphical environment to source code that can be executed to simulate testing on the DUT. The tool also allows a user to navigate between view modes that display the verification environment graphically, and that display the source code associated with components of the verification environment.

Claims22

Dependent claims

A computer processor configured to generate code simulating testing on an integrated circuit device, the processor being in communication with a user interface and a memory, the processor configured to execute:

an environment builder that displays a graphical environment model on the user interface, the graphical environment model displaying a device under test graphic, a verification graphic, and at least one connection graphic connecting the device under test graphic and the verification graphic, the device under test graphic associated with source code that simulates an integrated circuit device, the verification graphic associated with source code that simulates a verification module, and the at least one connection graphic being associated with source code that simulates connection signals between the verification module and the integrated circuit device;
a code generator that generates test simulation code that simulates operation of the integrated circuit device upon execution;
and
a navigation program that controls the display of source code associated with graphical environment model on the user interface,
wherein the navigation program controls the level of detail of the graphical environment model displayed via the user interface in response to receiving a detail control input signal via the user interface,
wherein the code generator is configured to generate a test simulation code in response to receiving an interface input signal, the test simulation code based at least in part on the source code associated with the verification graphic, the source code associated with the device under test graphic, and the source code associated with the at least one connection graphic, and
wherein the test simulation code is generated in a format for execution on a simulator to simulate testing on the integrated circuit device.

4 more elements

A method for generating test simulation code that is configured to simulate testing of an integrated circuit device upon execution, the method performed on a computer having a memory, a processor, and a user interface, the method comprising:

displaying a device under test graphic on the user interface as a component of a graphical environment model, the device under test graphic corresponding to source code that executes on a simulator to represent an integrated circuit device;
in response to receiving an add-graphic input signal, displaying at least one verification graphic as an element of a graphical environment model, each verification graphic associated with source code that executes on a simulator to simulate a verification model interacting with the integrated circuit device;
assigning, with the processor, at least one connection signal to the verification graphic in the graphical environment model, each connection signal corresponding to source code that executes on a simulator to represent a connection between the verification model and the integrated circuit device;
and
in response to receiving an interface input signal, generating with the processor a test simulation code based at least in part on the source code associated with the verification graphic and the assigned connection signal in the graphical environment model, the test code simulating the operation of the integrated circuit device upon execution on a simulator.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/293,466Filed 14 Oct 2016 · continuation
Priority: 13 Apr 2014
Published: US 2017/0032058 A12 Feb 2017
Granted: 5 Sep 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G06F 30/3323
Design verification, e.g. functional simulation or model checking: using formal methods, e.g. equivalence checking or property checking
G06F 30/33
Circuit design at the digital level: design verification, e.g. functional simulation or model checking
G06F 30/3308
Design verification, e.g. functional simulation or model checking: using simulation
G06F 30/367
Circuit design at the analogue level: design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE],…

Family

Application61/978,899Us provisional application · filed 13 Apr 2014
Application14/565,636Parent of this continuation · filed 10 Dec 2014
US 2017/0032058 A1Pre-grant publication · published 2 Feb 2017
US 9,501,594 B2Parent of this continuation
US 2015/0294061 A1Published application
US 9,754,059 B2This patent

From the US filing history. Foreign family members aren’t listed.