Cross-current power modelling using logic simulation
AssigneeInternational Business Machines Corporation
InventorsArun Joseph, Arya Madhusoodanan, Rahul M. Rao, Suriya T. Skariah
Life of this patent
Estimating the term…
Abstract
A processor may receive a transistor level integrated circuit (IC) design to be modelled. The processor may determine that the transistor level IC design has a first stage and a second stage. The processor may determine a first cross-current effective capacitance of the first stage and a second cross-current effective capacitance of the second stage. The processor may then determine a cross-current effective capacitance for the transistor level IC design by accumulating the first and second cross-current effective capacitances.
Claims20
A computer-implemented method for modelling cross-current power consumption in multi-stage transistor level integrated circuit (IC) designs, the method comprising:
- receiving, by a processor, a transistor level IC design to be modelled;
- determining that the transistor level IC design has two or more stages;
- determining a cross-current effective capacitance for each of the two or more stages wherein cross-current is crowbar current, and wherein the cross-current effective capacitance (Ceff) for each of the two or more stages is generated from the cross-current power consumption using the following equation:
- Ceff
- =
- P
-
- (
- slew
- ,
- Vdd
- )
- Vdd
-
-
- 2
- *
- f
- where P(slew, Vdd) is the cross-current power consumption as a function of a slew and a positive supply voltage Vdd as determined by circuit simulation, and f is an input signal frequency;
- and
- determining a cross-current effective capacitance for the transistor level IC design by accumulating the cross-current effective capacitances for the two or more stages,
- wherein the transistor level IC design is provided for fabrication of integrated circuits.
A system for modeling cross-current power consumption in multi-stage transistor level integrated circuit (IC) designs, the system comprising:
- a memory;
- a processor in communication with the memory, the processor being configured to perform a method comprising:
- receiving a transistor level IC design to be modelled;
- determining that the transistor level IC design has two or more stages;
- determining a cross-current effective capacitance for each of the two or more stages, wherein cross-current is crowbar current, and wherein the cross-current effective capacitance (Ceff) for each of the two or more stages is generated from the cross-current power consumption using the following equation:
- Ceff
- =
- P
-
- (
- slew
- ,
- Vdd
- )
- Vdd
-
-
- 2
- *
- f
- where P(slew, Vdd) is the cross-current power consumption as a function of a slew and a positive supply voltage Vdd as determined by circuit simulation, and f is an input signal frequency;
- and
- determining a cross-current effective capacitance for the transistor level IC design by accumulating the cross-current effective capacitances for the two or more stages,
- wherein the transistor level IC design is provided for fabrication of integrated circuits.
A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method comprising:
- generating a set of distinctive stages for a transistor level design library;
- generating, for each distinctive stage in the set of distinctive stages, a cross-current effective capacitance model parameterized by stage boundary conditions;
- receiving, by a processor, a transistor level IC design to be modelled;
- determining that the transistor level IC design has two or more stages;
- determining a cross-current effective capacitance for each of the two or more stages, wherein cross-current is crowbar current, and wherein the cross-current effective capacitance (Ceff) for each of the two or more stages is generated from the cross-current power consumption using the following equation:
- Ceff
- =
- P
-
- (
- slew
- ,
- Vdd
- )
- Vdd
-
-
- 2
- *
- f
- where P(slew, Vdd) is the cross-current power consumption as a function of a slew and a positive supply voltage Vdd as determined by circuit simulation, and f is an input signal frequency;
- and
- determining a cross-current effective capacitance for the transistor level IC design by accumulating the cross-current effective capacitances for the two or more stages,
- wherein the transistor level IC design is provided for fabrication of integrated circuits.
Dependencies are inferred from the claim text.