Gather using index array and finite state machine

An apparatus comprising:

• an index array;
• a finite state machine (FSM) operatively coupled with the index array to store a set of indices from a first single instruction multiple data (SIMD) register and a corresponding set of mask elements to facilitate a SIMD gather operation;
• an address generation logic to generate an address from an index of the set of indices in the index array for at least each corresponding mask element having a first value to access a first memory location corresponding to a first address generated to load a first data element;
• a merge data logic, operatively coupled with a second SIMD register, to write the first data element at a first in-register position in the second SIMD register according to a respective in-register position in the first SIMD register of an index corresponding to said first address generated.

A processor comprising:

• a first register comprising a plurality of mask elements, wherein the plurality of mask elements in the first register corresponds to a plurality of data elements accessible using a plurality of corresponding indices in a second register;
• a decoder to decode a first instruction to generate a set of micro-operations;
• and
• one or more execution units including:
• an index array to store a copy of the plurality of indices from the second register and the corresponding plurality of mask elements, and
• a finite state machine (FSM) operatively coupled with the index array to facilitate a gather operation using the plurality of indices and the corresponding mask elements,
• a merge data logic, operatively coupled with the memory access unit and with a third register, to write the first data element at a first in-register position in the third register according to a respective in-register position in the second register of an index corresponding to said first address generated.