Network interface device that maps host bus writes of configuration information for virtual NIDs into a small transactional memory

A network interface device (NID) for coupling to a host via a PCIe bus, wherein the NID implements a plurality of virtual NIDs, the NID comprising:

• a memory located on an island of an island-based network flow processor located on the NID that has a first portion and a second portion, the first portion stores configuration information for the plurality of virtual NIDs, wherein each virtual NID has a corresponding second block in the first portion that stores configuration information for the virtual NID, wherein the second portion does not store configuration information for any of the virtual NIDs;
• and
• an address translation circuit located on the island-based network flow processor, whereas if an access of the memory is a write into the first portion due to a PCIe write across the PCIe bus then the address translation circuit receives a portion of a PCIe address, wherein the portion of the PCIe address has A bits, wherein the address translation circuit deletes certain bits of the A bits and shifts other bits of the A bits thereby generating a smaller address of B bits, wherein A is greater than B, and wherein the B-bit address is then used to access the first portion of the memory, whereas if an access of the memory is a write into the second portion then the address translation circuit receives a B-bit address, does not delete bits and shift other bits of the B-bit address but rather supplies the same B-bit address to the memory to access the second portion;
• a bus interface circuit located on the island-based network flow processor coupled to the bus, wherein the PCIe address is received from the host via the bus interface circuit, and wherein the host is not located on the NID;
• and
• a physical network interface port, wherein the each of the plurality of virtual NIDs communicates through the same physical network interface port.

A method comprising:

• (a) receiving a request from a host via a bus onto an island based network flow processor, wherein the bus has a bus address space, wherein a Virtual Function (VF) portion of the bus address space is for communication with a plurality of virtual Network Interface Device (NID) functions, wherein the VF portion comprises a plurality of first blocks of bus address space, wherein the first blocks are located contiguously in bus address space, wherein each first block comprises a first portion and a second portion, wherein each first block comprises X address locations, wherein the request is a request to access an address location in a first portion of a selected one of the first blocks in the bus address space;
• (b) detecting that the request is a request to access an address location in the VF portion;
• (c) in response to the detecting of (b) translating an address of the request into a memory address, wherein the address of the request has more address bits than does the memory address;
• and
• (d) using the memory address to write virtual adapter configuration information into a memory location in a memory that is located on an island in the island based network flow processor, wherein the memory comprises a plurality of second blocks of memory locations, wherein each second block is for communication with a different one of the virtual NID functions, wherein the second blocks are located contiguously in the memory, wherein each second block has a first portion, wherein each second block comprises Y memory locations, wherein Y is less than X, wherein there is a one-to-one correspondence between each respective one of the first blocks and a corresponding one of the second blocks, wherein the memory location accessed in (d) is in a second block that corresponds to the address location in (a) in the first portion of the selected one of the first blocks, wherein (a), (b), (c) and (d) are performed by a NID coupled to the bus, and wherein the memory is a part of the NID.