US 9,753,858 B2 · DRAM cache with tags and data jointly stored in physical rows

Abstract

A system and method for efficient cache data access in a large row-based memory of a computing system. A computing system includes a processing unit and an integrated three-dimensional (3D) dynamic random access memory (DRAM). The processing unit uses the 3D DRAM as a cache. Each row of the multiple rows in the memory array banks of the 3D DRAM stores at least multiple cache tags and multiple corresponding cache lines indicated by the multiple cache tags. In response to receiving a memory request from the processing unit, the 3D DRAM performs a memory access according to the received memory request on a given cache line indicated by a cache tag within the received memory request. Rather than utilizing multiple DRAM transactions, a single, complex DRAM transaction may be used to reduce latency and power consumption.

Claims19

Dependent claims

A method comprising:

storing in a same row of a plurality of rows in a dynamic random access memory (DRAM) at least one or more cache tags and one or more cache lines indicated by the one or more cache tags;
receiving a memory request from a processing unit coupled to the DRAM;
and
in response to receiving the memory request, performing a memory access according to the received memory request on a given cache line indicated by a first cache tag within the received memory request, wherein performing the memory access comprises:
performing a single read of a respective row of the plurality of rows, wherein the respective row stores a plurality of cache tags and a plurality of cache lines;
copying said plurality of cache tags and said plurality of cache lines from the respective row to a row buffer prior to comparing the first cache tag to the plurality of cache tags stored in the respective row;
and
comparing a cache tag in the received memory request to the plurality of cache tags in the respective row.

5 more elements

A dynamic random access memory (DRAM) comprising:

a plurality of rows, wherein each row is configured to store at least (i) a plurality of cache tags and (ii) a plurality of cache lines indicated by the plurality of cache tags;
and
control circuitry configured to:
receive a memory request;
and
in response to receiving the memory request, perform a memory access according to the received memory request on a given cache line indicated by a first cache tag within the received memory request, wherein performing the memory access comprises:
performing a single read of a respective row of the plurality of rows, wherein the respective row stores a plurality of cache tags and a plurality of cache lines;
copying said plurality of cache tags and said plurality of cache lines from the respective row to a row buffer prior to comparing the first cache tag to the plurality of cache tags stored in the respective row;
and
comparing a cache tag in the received memory request to the plurality of cache tags in the respective row.

7 more elements

A system in package (SIP) comprising:

a processing unit on a first chip configured to generate memory requests;
and
a dynamic random access memory (DRAM) on a second chip comprising a plurality of rows, wherein the DRAM is coupled to the first chip and is configured to:
store in a same row of the plurality of rows at least a plurality of cache tags and a plurality of cache lines indicated by the plurality of cache tags;
receive a memory request from the processing unit;
and
perform a memory access according to the received memory request on a given cache line indicated by a first cache tag within the received memory request, wherein performing the memory access comprises:
performing a single read of a respective row of the plurality of rows, wherein the respective row stores a plurality of cache tags and a plurality of cache lines;
copying said plurality of cache tags and said plurality of cache lines from the respective row to a row buffer prior to comparing the first cache tag to the plurality of cache tags stored in the respective row;
wherein to perform the memory access, the DRAM is configured to perform the following operations as a block of uninterrupted operations:
perform a DRAM opening stage for the respective row;
store the plurality of cache tags and the plurality of cache lines in the row buffer;
copy back any data modified by the memory access and data unmodified by the memory access to the respective row;
and
perform a DRAM closing stage for the respective row.

12 more elements

Dependencies are inferred from the claim text.

DRAM cache with tags and data jointly stored in physical rows

Life of this patent

DRAM cache with tags and data jointly stored in physical rows

Life of this patent

Abstract

Claims19