Memory controller load balancing with configurable striping domains
AssigneeMellanox Technologies, Ltd.
InventorLiewei Bao
Life of this patent
Estimating the term…
Abstract
Managing data in a computing system comprising a plurality of cores includes: assigning an address within a memory address space for access by one of a plurality of memory controllers coupled to different respective cores based on a designated portion of the address. The designated portion is selected to exclude one or more highest order bits and bits that correspond to a cache line associated with the memory address. In response to a memory access request at one of the cores to access data stored at the address, the system determines which of the plurality of memory controllers to which the memory access request is to be directed based on the designated portion of the address.
Claims19
A method for managing data in a computing system comprising a plurality of cores, the method comprising:
- defining striping domains among a plurality of memory controllers in the computing system, to balance workloads within at least one of the defined striping domains;
- configuring by system software a pair of customizable striping mode bits to define striping modes for logical memory partitions for one or more of the striping domains, according to an application executing in the computing system to balance workloads within the one or more striping domains during execution of the application;
- assigning an address within a memory address space partitioned according to the logical memory partitions for access by a corresponding one of the plurality of memory controllers in the defined striping domain, and which plurality of memory controllers are coupled to different respective cores, with assigning based on a designated portion of the address that is selected to exclude one or more highest order bits and bits that correspond to a cache line associated with the memory address;
- receiving a memory access request at one of the cores to access data stored at the address;
- and
- determining in response to the memory access request based on the designated portion of the address, which of the plurality of memory controllers the memory access request is to be directed.
An integrated circuit that executes system software for configuring a computing system comprising a plurality of cores for causing the computing system to:
- define striping domains among a plurality of memory controllers of the computing system, to balance workloads within at least one of the defined striping domains;
- configure by the system software a pair of customizable striping mode bits to define striping modes for logical memory partitions for one or more of the striping domains, according to an application to execute on the computing system to balance workloads within the one or more striping domains during execution of the application;
- assign an address within a memory address space partitioned according to the logical memory partitions for access by a corresponding one of the plurality of memory controllers in the defined striping domain, and which plurality of memory controllers are coupled to different respective cores, with assignment based on a designated portion of the address that is selected to exclude one or more highest order bits and bits that correspond to a cache line associated with the memory address;
- receive a memory access request at one of the cores to access data stored at the address;
- and
- determine, in response to the memory access request based on the designated portion of the address, which of the plurality of memory controllers the memory access request is to be directed.
A computing system, comprising:
- a plurality of cores;
- a plurality of memory controllers coupled to different respective cores;
- and
- processors in the cores configured to:
- define striping domains among a plurality of memory controllers of the computing system, to balance workloads within at least one of the defined striping domains;
- configure by the system software a pair of customizable striping mode bits to define striping modes for logical memory partitions for one or more of the striping domains, according to an application to execute on the computing system to balance workloads within the one or more striping domains during execution of the application;
- assign an address within a memory address space partitioned according to the logical memory partitions for access by a corresponding one of the plurality of memory controllers in the defined striping domain, and which plurality of memory controllers are coupled to different respective cores, with assignment based on a designated portion of the address that is selected to exclude one or more highest order bits and bits that correspond to a cache line associated with the memory address;
- receive a memory access request at one of the cores to access data stored at the address;
- and
- determine, in response to the memory access request based on the designated portion of the address, which of the plurality of memory controllers the memory access request is to be directed.
Dependencies are inferred from the claim text.