Conditional pattern detector for detecting hangs

#This application is related to the following U.S. Non-Provisional Applications filed concurrently herewith, each of which is a national stage application under 35 U.S.C. 371 of the correspondingly indicated International Application filed Dec. 13, 2014, each of which is hereby incorporated by reference in its entirety.

#U.S. Non-Provisional Ser. No. International Application No. 14/891,337 PCT/IB2014/003174 14/891,338 PCT/IB2014/003149 14/891,339 PCT/IB2014/003181 14/891,340 PCT/IB2014/003196

#The invention relates to hang detection logic, and more particularly, to hang detection logic for a last level cache.

#FIG. 1 is a block diagram of one embodiment of a multi-core microprocessor having a shared LLC.

#FIG. 2 is a block diagram of the LLC of FIG. 1.

#FIG. 3 is a block diagram of one embodiment of a tagpipe staging architecture for the LLC of FIG. 2.

#Referring now to FIG. 1, a block diagram illustrating a multi-core microprocessor 100 is shown. The microprocessor 100 includes a plurality of processing cores 102, a shared last-level cache (LLC) memory 120, and a bus interface unit (BIU) 122.

#In the example embodiment of FIG. 1, there are four cores 102 denoted core 0 102-0, core 1 102-1, core 2 102-2 and core 3 102-3, which are collectively referred to as cores 102 and generically individually referred to as core 102. Each of cores 102-0, 102-1, 102-2, 102-3 accesses the LLC 120 via a respective interface 118-0, 118-1, 118-2, 118-3, which are referred to collectively as interfaces 118 and generically individually as interface 118. The bus interface unit 122 also accesses the LLC 120 via an interface 118-4. The microprocessor 100 is part of a larger computing system (not shown) that includes system memory and peripherals (also not shown), with which the LLC 120 communicates via the bus interface unit 122 over a system bus 124. Although the embodiment of FIG. 1 illustrates a processor 100 with four cores 102, other embodiments with different numbers of cores 102 are contemplated. All of the cores 102 share the LLC 106.

#Each processing core 102 comprises an instruction cache 104, an instruction translator 106 that includes microcode 108, execution units 110, architectural registers 112, and a memory subsystem 114 (e.g., a memory order buffer, data cache, and a table walk engine). The execution units 110 may include integer units, floating point units, media units, branch units, load units and store units. Other functional units (not shown) may include a table walk engine, which performs translation table walks to generate virtual to physical address translations; branch predictors; a rename unit; a reorder buffer; reservation stations; an instruction fetch unit; an instruction decoder; an instruction scheduler; an instruction dispatcher; data prefetch units; and non-architectural registers, among others. Various microarchitectural features may be included in the cores 102. For example, the cores 102 may be superscalar—capable of issuing multiple instructions per clock cycle to the execution units 110 for execution—or scalar. As another example, the cores 102 may execute instructions in-order or out-of-order, the latter enabling instructions to be issued for execution out of program order. In one embodiment, the cores 102 conform substantially to the x86 instruction set architecture, although the cores 102 are not limited to a particular instruction set architecture, and may include other memory request agents such as a graphic processing unit (GPU) or field programmable gate array (FPGA).