Techniques for handling errors in persistent memory
AssigneeIntel Corporation
InventorsMohan J. Kumar, Murugasamy K. Nachimuthu, Camille C. Raad
Life of this patent
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Abstract
Examples may include a basic input/output system (BIOS) for a computing platform communicating with a controller for a non-volatile dual in-line memory module (NVDIMM). Communication between the BIOS and the controller may include a request for the controller to scan and identify error locations in non-volatile memory at the NVDIMM. The non-volatile memory may be capable of providing persistent memory for the NVDIMM.
Claims21
An apparatus comprising:
- circuitry at a controller resident on a non-volatile dual in-line memory module (NVDIMM);
- a receive component for execution by the circuitry to receive an error scanning request;
- an error component for execution by the circuitry, responsive to the error scanning request, to scan a device physical address range for a non-volatile memory at the NVDIMM and identify uncorrected errors in the device physical address range, the non-volatile memory capable of providing persistent memory for the NVDIMM;
- and
- an indicate component for execution by the circuitry to indicate, via a first data structure resident at the NVDIMM, device physical addresses having the identified uncorrected errors to a basic input/output system (BIOS) for a computing platform coupled with the NVDIMM, the BIOS capable of accessing the first data structure to read the indicated device physical addresses and convert the device physical addresses to system physical addresses that are then maintained in a second data structure accessible to an operating system or device driver.
A method comprising:
- receiving, at a controller resident on a non-volatile dual in-line memory module (NVDIMM), an error scanning request;
- scanning a device physical address range for a non-volatile memory at the NVDIMM responsive to the error scanning request, the non-volatile memory capable of providing persistent memory for the NVDIMM;
- identifying uncorrected errors in the device physical address range;
- and
- indicating, via a first data structure resident at the NVDIMM, device physical addresses having the identified uncorrected errors to a basic input/output system (BIOS) for a computing platform coupled with the NVDIMM, the BIOS capable of accessing the first data structure to read the indicated device physical addresses and convert the device physical addresses to system physical addresses that are then maintained in a second data structure accessible to an operating system or device driver.
At least one non-transitory machine readable medium comprising a plurality of instructions that in response to being executed by a system having circuitry arranged to implement a basic input/output system (BIOS) for a computing platform cause the system to:
- send an error scanning request to a controller resident on a non-volatile dual in-line memory module (NVDIMM) coupled to the computing platform, the NVDIMM having a non-volatile memory capable of providing persistent memory for the NVDIMM;
- determine that the controller has completed scanning a device physical address range for the non-volatile memory responsive to the error scanning request;
- access a first data structure resident at the NVDIMM to read device physical addresses having identified uncorrected errors that were identified by the controller during the scanning of the device physical address range;
- convert the device physical addresses having identified uncorrected errors to system physical addresses having identified uncorrected errors, wherein at least one of the uncorrected errors is an uncorrectable error;
- and
- store the system physical addresses having identified uncorrected errors to a second data structure accessible to an operating system or device driver for the computing platform.
Dependencies are inferred from the claim text.