Multiple processor modes execution method and apparatus including signal handling

#The present disclosure relates to the field of computing. More particularly, the present disclosure relates to multiple processor modes execution method and apparatus, including signal handling.

#The background description provided herein is for the purpose of generally presenting the context of the disclosure. Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.

#With advances in integrated circuit and computing technologies, increasing number of processors support 64-bit addressing providing larger 64-bit address spaces and extra registers for user applications. Further, for a number of processors, it is possible for developers to port only key parts of a legacy 32-bit application to 64-bit code and run the ported portion in 64-bit processor mode, while leaving the remaining parts unmodified and running in 32-bit processor mode. The hybrid application would use mode switch instruction to switch between the 32-bit processor mode and the 64-bit processor mode to execute the 32-bit and 64-bit code segments.

#Embodiments of the multiple processor modes execution technique of the present disclosure may overcome this limitation. The technique will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

#FIG. 1 is a block diagram of a computing device incorporated with the multiple processor modes execution technique of the present disclosure, according to various embodiments.

#FIG. 2 illustrates preservation of the extra context during signal handling, according to various embodiments.

#Apparatuses, methods and storage media associated with multiple processor modes execution are described herein. In embodiments, an apparatus may include a processor with a plurality of processor modes, including a first processor mode to operate on first register file, and a second processor mode to operate on second register file, the second register file including the first register file. The apparatus may further include a signal handler to handle a signal from a kernel, in the first processor mode; and a signal handler wrapper to switch the processor to the second processor mode on delivery of the signal from the kernel, save a current extra context of the second processor mode from the second register file to a user stack, switch the processor back to the first processor mode, then invoke the signal handler to handle the signal.

#In embodiments, the signal handler wrapper, on handling of the signal by the signal handler, may further switch the processor to the second processor mode again to call a signal-return system call that restores all contexts including the saved extra context back to the second register file, and thereafter, resumes user code execution.

#In the following detailed description, reference is made to the accompanying drawings which form a part hereof wherein like numerals designate like parts throughout, and in which is shown by way of illustration embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of embodiments is defined by the appended claims and their equivalents.