Simultaneous multithreading resource sharing

#The present disclosure relates generally to the field of computer hardware, and more particularly to enabling simultaneous multithreading (SMT) resource sharing in reduced-thread modes.

#SMT is a technique for improving the efficiency of computer processor using hardware multithreading by exploiting thread-level parallelism. SMT permits multiple independent execution threads to better utilize shared resources such as cache, buffers, queues, and execution units. In addition to the shared resources, each hardware thread in a processor that supports SMT has its own architected resources, including one or more sets of registers.

#Embodiments of the present disclosure include a method and a system for using simultaneous multithreading (SMT) architected resources in a reduced-thread mode. A computer system may determine a mode for a processor. The processor may support SMT, and it may have a first hardware thread with a first architected resource and a second hardware thread with a second architected resource. The computer system may determine that the processor is in a reduced-thread mode. The computer system may determine that the first hardware thread is a primary hardware thread that is active in the reduced-thread mode, and that the second hardware thread is a secondary hardware thread that is inactive in the reduced-thread mode. The computer system may disable the second hardware thread. The computer system may enable the first hardware thread to access the second architected resources.

#The drawings included in the present disclosure are incorporated into, and form part of, the specification. They illustrate embodiments of the present disclosure and, along with the description, serve to explain the principles of the disclosure. The drawings are only illustrative of typical embodiments and do not limit the disclosure.

#FIG. 1 illustrates a block diagram of a processor core that supports simultaneous multithreading (SMT) with two hardware threads, in accordance with embodiments of the present disclosure.

#FIG. 2 illustrates a flowchart of a method for enabling SMT resource sharing of architected resources in a reduced-thread mode, in accordance with embodiments of the present disclosure.

#While the embodiments described herein are amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the particular embodiments described are not to be taken in a limiting sense. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

#Aspects of the present disclosure relate generally to the field of computer hardware, and in particular to enabling simultaneous multithreading (SMT) resource sharing in reduced-thread modes. While the present disclosure is not necessarily limited to such applications, various aspects of the disclosure may be appreciated through a discussion of various examples using this context.

#Each hardware thread in a processor that supports multithreading (such as SMT) has its own set of architected resources. The architected resources may include one or more sets of registers, such as general purpose registers and/or vector/scalar registers. These registers may be used by the hardware threads when executing parts of an application in parallel. The use of registers allows hardware threads to simultaneously perform operations on data without interfering with other hardware threads working with the same data.