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US 9,753,752 B2Granted
Simulator generation method and apparatus
AssigneeHuawei Technologies Co., Ltd.
InventorsHandong Ye, Peng Zhao, Senhuo Zheng, Jiong Cao
Life of this patent
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Abstract
The present invention discloses a simulator generation method and apparatus, relating to the field of simulator generation, which are used to implement rapid portability and high efficiency of a simulator. The solutions in the present invention are applicable to simulator generation.
Claims13
A method, comprising:
- obtaining an instruction set configuration file;
- generating a decoding table and a decoding algorithm according to the instruction set configuration file, wherein the decoding table comprises:
- an instruction code table, an instruction description table, and a bit field table, and assembly instruction operation code is recorded in the instruction code table, information of each piece of the assembly instruction operation code is recorded in the instruction description table, and a method for calculating a numerical value in each operand bit field is recorded in the bit field table;
- generating a simulator according to the decoding table, the decoding algorithm, and module code, wherein the simulator is configured for simulating an action associated with a chip during a chip design process, wherein the module code is code used to simulate an action of an assembly instruction and code of a second algorithm in a decoding process;
- performing the chip design process, wherein performing the chip design process comprises executing the simulator code to simulate the action;
- and
- manufacturing the chip according to the chip design process.
4 more elements
An apparatus, comprising:
- an obtaining unit, configured to obtain an instruction set configuration file;
- an interpreter, configured to generate a decoding table and a decoding algorithm according to the instruction set configuration file, wherein the decoding table comprises:
- an instruction code table, an instruction description table, and a bit field table, and assembly instruction operation code is recorded in the instruction code table, information of each piece of the assembly instruction operation code is recorded in the instruction description table, and a method for calculating a numerical value in each operand bit field is recorded in the bit field table;
- and
- a compiler, configured to generate a simulator according to the decoding table, the decoding algorithm, and module code, wherein the simulator is configured for simulating an action associated with a chip during a chip design process, wherein the module code is code used to simulate an action of an assembly instruction and code of a second algorithm in a decoding process,
- wherein the apparatus is configured to perform the chip design process and manufacture the chip according to the chip design process, wherein performing the chip design process comprises executing the simulator code to simulate the action.
3 more elements
Dependencies are inferred from the claim text.