Thread issue control

#This application is claims priority to GB Application No. 1402259.4, filed 10 Feb. 2014, the entire content of which is hereby incorporated by reference.

#Field

#The present technique relates to the field of data processing systems. More particularly, it relates to the control of thread issue into a processing pipeline within a data processing system.

#FIG. 1 schematically illustrates a data processing system including a processing pipeline and an issue controller for issuing threads in accordance with both a pilot sequence and a main sequence which differ from a predetermined logical sequence;

#FIG. 2 schematically illustrates a predetermined logical sequence of thread issue;

#FIG. 3 schematically illustrates issue in accordance with a pilot sequence and a main sequence;

#FIG. 1 schematically illustrates a data processing system 2 including a graphics processing unit 4 and a main memory 6. The graphics processing unit 4 includes a processing pipeline 8, a cache memory 10, a stall manager 12 and an issue controller 14. It will be appreciated that in practice the graphics processing unit 4 will typically include many further data processing elements, such as those which create threads received by the issue controller 14 and queued therein prior to issue to the processing pipeline 8. Such additional circuit elements have been omitted from FIG. 1 for the sake of clarity. When a thread (e.g. a sequence of program instructions executing to generate a particular value, such as a particular pixel fragment within an array of pixels) executing within the processing pipeline 8 accesses a data value, then a check is made as to whether or not that data value is held within the cache memory 10. If the data value is not held within the cache memory 10, then a cache miss arises and a cache line including that data value is fetched from the main memory 6 to the cache memory 10. This fetch from the main memory 6 is relatively slow and has a memory latency time associated with it which may be several hundred times greater than the time normally taken to access a data value within the cache memory 10. A thread will circulate within the processing pipeline 8 with its successive instructions being executed until the thread has finished at which point it will be retired from the processing pipeline 8 freeing up a slot into which another thread may be issued.

#The processing pipeline 8 executes a plurality of threads in parallel. The threads are issued into the processing pipeline 8 by the issue controller 14 in dependence upon issue queue data 16 (priority values, time stamps etc) associated with the queued threads. The issue controller 14 receives the threads in the predetermined logical sequence in which they are generated by the software and/or upstream hardware. The issue controller 14 issues the threads to the processing pipeline 8 following both a main sequence and pilot sequence. Threads are selected from the main sequence in the main sequence order. Threads are selected from the pilot sequence in the pilot sequence order. Selection as to whether the next thread to be issued should be taken from the main sequence or the pilot sequence is made in accordance with the issue queue data 16 as will be described later. The issue controller 14 may be considered to hold two queues, namely a pilot sequence queue and a main sequence queue. Threads are issued from each of these queues in their respective order, and a selection is made as to from which queue the next thread is to be issued in dependence upon the issue queue data 16. The issue queue(s) may be provided for other reasons in addition to the above (e.g. forward pixel kill) and so support for the present techniques may be added with little extra overhead.

#When a thread is progressing along the processing pipeline 8 and a cache miss occurs, then the stall manager 12 coupled to the processing pipeline 8 serves to stall that thread until the data value which missed has been fetched to the cache memory 10 whereupon the thread is unstalled. The thread (or at least the relevant stalled instruction of the thread) may be recirculated within the pipeline 8 while it is stalled and its partial processing state retained.